Senior DFT Design Engineer

Folsom, CA 95630
  • Job Code
Job Description

Are you passionate about computer graphics and disrupting the industry with your innovation, and working with leading Engineers on Intel's latest GPU architecture. Do you love collaborating with diverse teams to help achieve best-In-class visual experiences that enable users to immerse themselves in a new visual future? Then the Graphics and Throughput Computing Hardware Engineering (GTCHE) team at Intel has opportunities for you. Our Hardware development team designs and validates the future processors that are the engines behind our GPUs. We are looking for DFT Engineers to join our team who are ready to make significant impacts on the future of graphics and visual computing technology.


As a member of the Graphics Hardware DFT group you will be responsible for one or more of the following activities:

  • You will work on the design, RTL/GLS validation, automation and/or timing analysis in the following DFT domains: TAP Controller, Scan, Array DFT (PBIST/MBIST), IO DFT, PLL DFT or HVM Reset
  • You will also contribute or be involved with trace pattern generation efforts as well as post-silicon enabling debug support and/or analysis of the DFT features and content types you are responsible for

We are looking for candidates who have:

  • Strong written and verbal communication skills
  • Strong leadership in driving execution across different functional teams and global teams
  • Possesses strong teamwork, problem solving and influencing skills along with abilities to work with different geographical locations


Minimum skills and Experience:

Bachelors in Electrical/Computer Engineering or related field with 5+ years of industry experience.  Or a Masters in the same fields with 2+ years of industry experience.   

Your experience should be in the following:

  • At least one of the key DFT features such as TAP/JTAG, Scan/ATPG or Array DFT (MBIST/PBIST)
  • SoC IP DFT design integration or verification
  • EDA tools such as ATPG tools, Mentor Tessent shell, VCS simulation and/or debug tools.
  • Silicon enabling debug or test pattern development experience

Preferred Skills and Experience:

  • Design automation skills and proficiency in programming or scripting languages
  • Structural design flows, including timing, routing, placement or clocking analysis
  • High volume manufacturing requirements and test flows
  • 3D, media and display graphics pipelines
  • SoC architecture

Inside this Business Group

Intel Architecture, Graphics, and Software (IAGS) brings Intel's technical strategy to life. We have embraced the new reality of competing at a product and solution levelnot just a transistor one. We take pride in reshaping the status quo and thinking exponentially to achieve what's never been done before. We've also built a culture of continuous learning and persistent leadership that provides opportunities to practice until perfection and filter ambitious ideas into execution.

Other Locations

US, California, Santa Clara

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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Senior DFT Design Engineer

Folsom, CA 95630

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