Senior Chipsets Logic Design Manager

Intel
Folsom, CA 95630
  • Job Code
    JR0180036
Job Description

Seize the opportunity to work with the team responsible for RTL logic design and microarchitecture of chipsets for PCs millions of people around the world will use. The Chipsets Logic Team, CLT is part of the Chipsets Silicon Group, CSG within Design Engineering Group, DEG and is responsible for developing soft IPs, subsystems and gaskets for client and server chipsets.

This job requisition is to seek an experienced, disciplined and collaborative Engineering Manager to lead and strengthen the CLT team in Folsom, CA (Santa Clara and Chandler will also be considered).

The candidate is expected to be skillful and hands-on, capable to execute and willing to get hands dirty.

Responsibilities include but are not limited to:

  • Set priorities for the team, get results across boundaries, ensure an inclusive work environment, develop employees, and manage performance.

  • Lead and mentor the team in architecture/micro-architecture definition, design, verification, and documentation for soft IP development.

  • Exercise judgment and discretion to develop solutions, remove obstacles and redefine approaches.

  • Assess risks and identify solutions to timely, efficient achievement of project goals.

  • Ensure that quality standards and development resource constraints are met.

  • Influence business unit or cross organizational strategies relevant to project goals.

  • Have an advanced understanding of the technical concepts, architecture, systems, development methods, and disciplines associated with the defined project, and utilizes knowledge to accelerate project completion.

  • Guide and coach the team to define module interfaces/formats for simulation; perform Logic design for soft IP and subsystems, Register Transfer Level coding, and simulation; perform all aspects of the soft IP design flow from high level design to synthesis, timing and power to create high quality soft IP.


Qualifications

  • The candidate must possess a minimum of Bachelors Degree in Electrical Engineering, Electronics Engineering, Computer Engineering, Computer Science or equivalent.

  • The candidate must have a successful track record of hardware development experience and demonstrated leadership skills in managing IP development or SOC integration team.

  • The candidate must have demonstrated the ability to solve highly complex technical problems with excellent communication skills and the ability to motivate the organization.

  • The candidate must also have demonstrated strong ethical standards and be able to set the tone from the top. Must also be able to lead in a highly ambiguous and dynamic business environment.


Other technical requirements:

  • 10+ years of relevant experience in pre-silicon logic design and validation, experienced with multiple project cycles.

  • experienced in VLSI or Structural and Physical design flow and methodology, SIP (soft IP) and HIP (hard IP) interoperability validation.

  • experienced in Power-aware design and validation flows.

  • experienced in defining architecture or microarchitecture

  • experienced with various IP development processes and methodologies including but not limited to:

- design and verification with System Verilog,

- simulation/emulation and debug with major EDA tools,
- RTL model build and testbench development flow,
- design for test, design for verification,
- structural design flows, performance verification, scan coverage.

Inside this Business Group

The Devices Development Group (DDG) is a global organization focused on the development and integration of SOCs, critical IPs including Atom and chipsets that power Intel's leadership products. This business group leverages an incomparable mix of experts with different backgrounds, cultures, perspectives, and experiences to unleash the most innovative, amazing, and exciting computing experiences.



Other Locations

US, Arizona, Phoenix;US, California, Santa Clara



Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.



Position of Trust

This role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter....

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Senior Chipsets Logic Design Manager

Intel
Folsom, CA 95630

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