Senior Assembly Integration Engineer

Intel
Santa Clara, CA 95050
  • Job Code
    JR0185323
Job Description

Intel's Silicon Photonic Product Division (SPPD) is looking for an experienced Assembly/Packaging Process Integration Engineer to own health of all products coming out of OSATs (Outsourced Assembly and Test). Primary Responsibilities include own and deliver NPI and Production die to meet SPPD cost, quality/yield, and output targets with specific focus on OSATs.

Responsibilities will include but not limited to:

  • Work with OSATs to resolve Quality/Yield issues.
  • Drive continuous improvement roadmaps for Yield, Quality and Cost projects.
  • Work with OSATS to establish capacity to meet SPPD product demand.
  • Implement Process Control Systems to prevent excursions.
  • Drive 8Ds at OSATs to capture learnings, improve processes and systems.
  • Act as divisional POC for OSATs.
  • Debug assembly process/ test/ product interactions to find solutions..
  • Work with Development Engineering and other Fab Ops team members for transferring process/products from development to manufacturing, NPIs and for managing excursions.
  • Debug and resolve complex excursions and yield limiters by providing assembly process expertise.
     

In this position you will gain invaluable experience which will allow growth and expanded opportunities within this business group as well as future possible opportunities with other business groups within Intel.


Qualifications

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Education Requirement:

Bachelors degree with 4+ years of experience working in the areas of IC packaging and assembly.
 

Minimum Qualifications

  • 4+ years of experience in assembly processes for flipchip, wirebond, underfill, chip-on-chip, die prep, singulation, Heat sink attach and other semiconductor IC packaging assembly processes.
  • 4+ years of experience working on TD and/or HVM semiconductor IC assembly/packaging process.


Preferred Qualifications

  • Masters degree with 6+ years of experience or a PhD with 4+ years of experience working in the areas of IC packaging and assembly.
  • 2+ years of experience working with OSAT partners.
  • 3+ years of experience in sustaining and continuous improvement of HVM processes & products.
  • 2+ years of experience advanced packaging technologies and assembly processes.
  • 2+ years of experience in debugging/resolving complex issues related to product/process/test interactions.
  • 2+ years of experience using statistical tools and software such as JMP, or SQL.
  • 1+ years of experience with silicon photonic fabrication and optical device.

Inside this Business Group

The Data Center Group (DCG) is at the heart of Intels transformation from a PC company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologiesspanning software, processors, storage, I/O, and networking solutionsthat fuel cloud, communications, enterprise, and government data centers around the world.



Other Locations

US, Arizona, Phoenix



Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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Senior Assembly Integration Engineer

Intel
Santa Clara, CA 95050

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