Scan DFT Methodology Engineer

Intel
Santa Clara, CA 95050
  • Job Code
    JR0185442
Job Description

As a Scan DFT Methodology Engineer, you will develop tools, flows, and methodology for design-for-test, test generation, and test content delivery to manufacturing.

You will deploy scan solutions to Intel's design teams across all product segments and work closely with EDA tool vendors to define requirements for next generation products.

You will partner with design, manufacturing and methodology teams to continuously improve design efficiency, test quality, and manufacturing cost.

You will collaborate with an interdisciplinary team spanning chip design, product development and process technology development.


Qualifications

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

The candidate must possess a Bachelor's degree in Electrical/Electronic Engineering, Computer Science or a related field with 4+ years experience -OR- a Master's degree in Electrical/Electronic Engineering, Computer Science or a related field with 3+ years experience -OR- a PhD in Electrical/Electronic Engineering, Computer Science or a related field with 1+ years experience in the following:

  • DFT flow/methodology development
  • Scan DFT concepts, architecture, and methodology
  • Scan insertion, scan compression, ATPG, coverage and DRC analysis using industry standard tools (eg. Tessent DFT tools or comparable commercial solutions)
  • Perl or TCL scripting

Preferred Qualifications:

Experience in:

  • VLSI design flow including synthesis, physical design, formal verification, and timing analysis
  • Developing efficient, robust, and scalable design automation software
  • Software engineering practices including code quality, revision control, debugging skills and agile methodology

Inside this Business Group

In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intels products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moores Law and groundbreaking innovations.  DEG is Intels engineering group, supplying silicon to business units as well as other engineering teams.  As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.



Other Locations

US, California, Folsom;US, Colorado, Fort Collins;US, Oregon, Hillsboro


Intel Corporation will require all new U.S. employees to be fully-vaccinated for Covid-19 as a condition of hire unless they have an approved accommodation in place under applicable law. Newly-hired employees will be required to provide proof of vaccination prior to their start date.



Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Annual Salary Range for jobs which could be performed in US, Colorado:
$111,000.00-$166,390.00


Benefits:
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, and benefit programs. Find more information about our Amazing Benefits here

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Scan DFT Methodology Engineer

Intel
Santa Clara, CA 95050

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