RTL Design Engineer

Santa Clara, CA 95050
  • Job Code
Job Description

In this role responsibilities include, although are not limited to:

  • Participate in Subsystem and IP RTL logic designs (in Verilog, system Verilog and other hardware description languages), functional validation, timing constraint generation and synthesizing the RTL for physical implementation through auto place and route.
  • Performs all aspects of RTL designs to ensure best in class area, power and timing.
  • You will also be responsible to ensure successful integration of the subsystem/IP into fullchip hardware and software.


You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your schoolwork/classes/research and/or relevant previous job and/or internship experiences. This is an entry level position and will be compensated accordingly.     

Minimum Qualifications:

Candidate must have a Master's degree in Electrical Engineering with:

  • Micro-architecture trade-offs and documentation
  • Low-power design using UPF and clock gating
  • Multiple clock domain design
  • State machine design
  • Simulation and debug experience using VCS/Verdi
  • Synthesis and speed path debug
  • Perl / C-shell


Inside this Business Group

IP Engineering Group's (IPG) vision Build IPs that power Intel's leadership products and power our customer's silicon. We want to attract & retain talent who get joy in building high quality IP and share our core belief that IP is fundamental to transforming Intel's silicon design process. IPG's guiding principles will be ensuring Quality (Zero Bugs), Customer Obsession (Delight our Customers) and structured Problem Solving. We are a fearless organization transforming IP development.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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RTL Design Engineer

Santa Clara, CA 95050

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