PROM Physical Design Engineer

Intel
Austin, TX 78701
  • Job Code
    JR0184021
Job Description

About the Organization:

You will be part of Intel Advanced Design Organization (AD) within Design Enablement (DE) focused on pathfinding and development of advanced memory technology and circuits to enable best-in-class memory collateral/IP and product design across all generations of Intel process technology.

About the role:

You will be involved in deep sub-micron IC physical design in Intel's leading process technology, creating and implementing competitive solutions with Intel's PROM circuit technology for use in mobile, IOT, client, and server segments.

Job responsibilities include:

  • Hard IP physical design planning

  • Implementation and verification, as well as managing layout development

  • Clear documentation, and communication regarding Hard IP

  • Managing and delivering various project/product requests

Important behavior traits we look for:

  • Clear documentation and communication skills: thorough concise, effective documentation of provided solutions is expected, as well as timely communication with customers, and careful consideration of customer requests.


Qualifications

You must possess the below requirements to be initially considered for this position. Preferred qualifications are in addition to the requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:
Bachelor's degree in EE/CE or related STEM major with 3+ years experience in semiconductor industry OR Master's degree in EE/CE or related STEM major with 2+ years experience.

Experience in VLSI design, specifically Hard IP physical design and methodology, including but not limited to:

  • Feature and specification definition of potential physical design solutions of analog and mixed-signal circuits

  • Exploration of novel, robust, competitive physical design solutions (considering power delivery, area and routing for performance) through feasibility studies

  • Physical verification of layout quality through layout-extracted static timing analysis

  • Reliability verification of layout: IR drop, electro-migration and self-heat analysis

Preferred Qualifications:

  • Experience in physical design convergence using industry standard physical design and validation tools.

  • Knowledge of layout, layout strategies, and techniques (including analog techniques) to minimize variance, noise, and maximize reliability.

  • Knowledge of deep sub-micron integrated circuit (IC) layout design and verification principles, especially as it applies to memory arrays.

  • Knowledge of process technology is recommended.

  • Experience in scripting languages (perl, tcl, etc.) to enhance layout design automation, verification, and delivery is recommended.

  • Knowledge of design synthesis Design Compiler (DC) and Integrated Circuit Compiler (ICC) and mixed design implementation (synthesis with Hard IP)

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Inside this Business Group

As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moores Law to bring smart, connected devices to every person on Earth



Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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PROM Physical Design Engineer

Intel
Austin, TX 78701

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