Product Development Engineer - DFX/Reset/Vector/Fuse

Intel
Santa Clara, CA 95050
  • Job Code
    JR0180434
Job Description

The MPE DRV and Fuse team in Santa Clara and Austin is looking for a motivated Engineer to join the team to work in the highly challenging environment of product development across Intel's server families In this position the engineer gets the unique opportunity to work right from the early stages of design to finally taking the product to silicon and powering it on Engineers work on architecture definitions creating test plans and pre-silicon test cases and validate them in a simulation emulation environment.

The team is responsible for developing the DFT and HVM Reset flows needed for manufacturing and taking them through production ramp.

In this role responsibilities include, although not limited to:

  • Ensures the testability and manufacturability of integrated circuits from the component feasibility stage through production ramp
  • Make significant contributions to design, development and validation of testability circuits
  • Evaluation, development and debug of complex test methods
  • Develops and debugs complex software programs to convert design validation vectors and drive complex test equipment
  • Creates and tests validation and production test hardware solutions
  • Tests, validates, modifies and redesigns circuits to guarantee component margin to specification
  • Analyzes and evaluates component specification versus performance to ensure optimal match of component requirements with production equipment capability with specific emphasis on yield analysis and bin split capability
  • Analyzes early customer returns with emphasis on driving test hole closure activities
  • Creates and applies concepts for optimizing component production relative to both quality and cost constraints
  • DFT Design Design for Test Pre-Silicon validation of reset test content at IP and full chip level including test writing
  • Test content generation of patterns to support HVM testers
  • Silicon debug to identify functional and DFT related bugs and silicon characterization to validate IP Support platform and system level validation teams to identify and close silicon issues
  • Analysis and disposition of early customer returns to drive understanding of design marginalities or develop test content to screen these units where needed
  • Work with Sort and Class team to deliver high quality test content and support improving PHIs

The ideal candidate should exhibit the following behavioral traits:

  • Excellent communication skills
  • Self motivated
  • Detailed oriented
  • Flexible to cross trained into respective functional areas


Qualifications

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

The candidate must possess a Bachelor's in Electrical/Electronic Engineering, Computer Engineering, Computer Science or a related field with 3+ years of experience -OR- a Master's degree in Electrical/Electronic Engineering, Computer Engineering, Computer Science or a related field with 2+ years experience in the following:

  • Logic validation and characterization
  • Experience in programming languages: Perl, python, or C++
  • Experience in DFT, hardware testing methods and tools

Preferred Qualifications:

  • Hardware architecture, logic/Circuit design and implementation

Inside this Business Group

The Infrastructure and Platform Solutions Group (IPSG) builds the silicon and platform infrastructure for Intel's silicon design teams. IPSG is comprised of a reusable pool of infrastructure IP blocks, design enabling services such as tools and automation, and a best-in-class post silicon ecosystem that ramps quickly to high volume manufacturing and validation. Our primary mission is to protect Intel's brand by providing the infrastructure necessary to enable all of Intel's products to hit the market on a dependable and predictable cadence.



Other Locations

US, Texas, Austin



Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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Product Development Engineer - DFX/Reset/Vector/Fuse

Intel
Santa Clara, CA 95050

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