PreSilicon cluster level validation engineer

Austin, TX 78701
  • Job Code
Job Description

The Austin Efficient CPU Design group is hiring pre silicon validation engineers to help develop new processor products. This is a great opportunity to join the front-end design validation team in a pre-Si verification role, early in the product lifecycle, as we enter the technology readiness (TR) phase, then move into design and execution.

This program will include innovation in system design and new system interconnect options to achieve performance and scalability, touching a broad scope of system components including computing (core/un-core), interconnect fabric, I/O and interrupt handling and power management. 

Job responsibilities will be tailored to the candidate's skills and expertise and will include several of the following, but not be limited to:

  • Ensuring the logic design meets the architectural specifications

  • Creating and optimizing the validation environment, tools, and methodologies

  • Use System Verilog for developing monitors, checkers and agents in the test environment

  • Developing or using checking software to compare model behavior against a specification

  • Generating focused and random test cases, analyzing coverage, and debugging failure cases

  • Writing software to provide controllability and observability into the model

  • Analyzing micro-architectural features to identify possible problem areas and create validation plans to address them

  • Desired behavioral traits of successful candidate include:Ability to work independently and at various levels of abstraction

  • Ability to work effectively with both internal and external teams/customers is expected.

  • Capable of working in a high performing team to deliver the results required from the organization.

  • Facilitator of direct and open communication, diversity of opinion, and debate


Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:
Must have at least a BS (MS Preferred) in Electrical Engineering, Computer Engineering, or Computer Science and BS with 4+ years of experience OR MS with 3+ in the validation of ASIC's or IP blocks or SOC's, and:
UVM/OVM testbench experience.

At least 3+ years of experience in:

  • Strong background in computer architecture such as pipelined systems, cache subsystems and coherency

  • Background and understanding of system architecture such as I/O connectivity and interrupt handling

  • Demonstrable experience writing System Verilog

  • Programming experience in C++, Perl

  • Familiarity with a range of internal and 3rd-party logic and design verification tools

  • Experience with SoC integration and/or verification

  • Experience developing testbench components such as: BFMs, monitors, checkers, etc.

Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.

Inside this Business Group

In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intels products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moores Law and groundbreaking innovations.  DEG is Intels engineering group, supplying silicon to business units as well as other engineering teams.  As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.

Intel Corporation will require all new U.S. employees to be fully-vaccinated for Covid-19 as a condition of hire unless they have an approved accommodation in place under applicable law. Newly-hired employees will be required to provide proof of vaccination prior to their start date.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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PreSilicon cluster level validation engineer

Austin, TX 78701

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