Pre-Si Verification Methodology Manager

Intel
Folsom, CA 95630
  • Job Code
    JR0183601
Job Description

The Graphics and Throughput Computing Hardware Engineering (GTCHE), organization is responsible for the development of Graphics IPs and discrete GPU SOCs. The FE-TFM team within GTCHE is responsible for providing methodologies for Best-In-Class RTL development, IP delivery, SOC integration and execution, and verification. The team develops and deploys these methodologies across all graphics IPs and SOCs. We are looking for a talented Pre-Si Verification Methodology Manager to join our team. In this position, you will lead the team that works on Verification  flows across clusters, IP, Subsystems, SOC and emulation to identify areas of methodology improvement through future trends or IP/SOC team needs. You will rapidly take features from concept to production and provide customer support, debug failures, and provide out of the box solutions.

The ideal candidate will have the following skills in addition to the qualifications listed below.

  • Must be a team player, with a demonstrated expertise to technically influence others.
  • Excellent analytical and problem-solving skills.
  • Strong verbal and written communication skills.


Qualifications

Minimum Skill and Experience:

Must have a Bachelors in Electrical/Computer Engineering, Computer Science or related field with 10+ years of industry experience. Or a Masters in the same fields with 6+ years of industry experience.
 

Your experience should be in the following:

  • IP,  SOC or ASIC development experience
  • Verification methodologies like OVM, UVM
  • Pre-Si Verification such as test plan writing, regressions, coverage analysis, Gate level simulations or emulation

In Addition to the above, you must have 5+ years of experience with managing or lead a team in the Semiconductor industry in one of these domains:

  • Cluster, IP, Subsystem, SOC level verification, FrontEnd DA, EDA development or AE for pre-silicon verification teams

 

Preferred skills and experience:

  • Technical RTL Verification or Front End Infrastructure Design methodology expertise
  • Knowledge of latest advancements in IP or SoC Front End Design tools flows and methodologies
  • Experience with developing validation testbenches, BFMs and infrastructure
  • Experience with System Verilog
  • Interaction with vendors that supply tools to support the Front End RTL development and verification flows

Inside this Business Group

Intel Architecture, Graphics, and Software (IAGS) brings Intel's technical strategy to life. We have embraced the new reality of competing at a product and solution levelnot just a transistor one. We take pride in reshaping the status quo and thinking exponentially to achieve what's never been done before. We've also built a culture of continuous learning and persistent leadership that provides opportunities to practice until perfection and filter ambitious ideas into execution.



Other Locations

US, Arizona, Phoenix;US, California, Santa Clara



Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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Pre-Si Verification Methodology Manager

Intel
Folsom, CA 95630

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