Pre-Si Validation/Verification Engineer

Folsom, CA 95630
  • Job Code
Job Description

We are looking for a highly motivated Pre-Silicon Validation Engineer who will be responsible for the definition and implementation of functional and DFx tests for client and server chipsets in cutting edge internal and external technology nodes. In this the scope of learning opportunity, contributions and influence expands over on-die, multi-die and system level clocking solutions.

Key responsibilities of the role include, although not limited to:

  • Develop validation environments including checkers, monitors and test suites-
  • Execute test plans by writing random & pseudo random stimulus and directed tests-
  • Debug failures on simulation / emulation / post silicon, file bugs and validate fixes-
  • Feature evaluations for complexity & effort working with design and architecture team, writing test plans-
  • Participate in improvements to the validation environment that drive down validation escape bug rates-
  • Supporting debug of failures for customers

The role requires the following attributes and previous experience:

  • Technical leadership with good communication, interpersonal and problem-solving skills
  • Motivated, self-directed and skilled at working effectively both independently and as a team
  • Hands-on verification experience and proficiency using System Verilog and strong proficiency using OVM/UVM.
  • Proven track record in pre-silicon verification from environment development to test development.
  • Willingness to work in a dynamic environment with abstract requirements.
  • Experience with implementation and use modern verification environments that include use of constrained-random stimulus and use of functional coverage


You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications

Candidate must have a Bachelor's degree in Electrical/Computer Engineering and 3+ years of experience in: - OR - a Master's degree in Electrical/Computer Engineering and 2+ years of experience in:

  • Reading and interpreting technical specs and Register Transfer Level (RTL) code.
  • Working on IP or SoC development, verification, integration using Verilog/System Verilog/ Open Verification Methodology (OVM)/Universal Verification Methodology (UVM).
  • Debug, writing monitors/checkers/reference models / stimulus

Preferred Qualifications

Experience with:

  • Simulation/debug tools like VCS / Verdi
  • Post silicon debugging experience

Inside this Business Group

The Devices Development Group (DDG) is a global organization focused on the development and integration of SOCs, critical IPs including Atom and chipsets that power Intel's leadership products. This business group leverages an incomparable mix of experts with different backgrounds, cultures, perspectives, and experiences to unleash the most innovative, amazing, and exciting computing experiences.

Other Locations

US, California, Santa Clara

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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Pre-Si Validation/Verification Engineer

Folsom, CA 95630

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