Pre-Si Validation Engineer

Santa Clara, CA 95050
  • Job Code
Job Description

The Security Architecture Engineering (SAE) team delivers both architecture and implementation on four pillars: foundational security, workload protection, software reliability and security assurance.

SAE is also chartered with understanding the next generation of security threats and technologies, while guiding future research and architecture decisions to secure Intels platforms while fostering a security first culture into Intel's product development and strategic practices.

As a senior member of the pre-silicon verification team for the Security IP and it's blocks you will be responsible for the Architecture and developments of Pre-Silicon functional validation collateral to verify system will meet design requirements. You will help to create and execute test plans for RTL validation, defining and running system simulation models, and finding and implementing corrective measures for failing RTL tests as well as analyzing and uses results to modify testing.

The responsibilities will include but not be limited to:

  • Defining, implementing, and deploying verification capabilities, methodologies, and process improvements

  • Development and execution of test-plans, test-bench components (BFMs, checkers, trackers, scoreboards) and functional coverage

  • Working closely with other verification engineers, RTL design engineers, micro-architects, and other team members to ensure quality of test-plans, verification environment, and tests

  • Strong discipline and attention to detail in ensuring high quality verification that minimizes bug escapes to higher levels of validation

  • Mentorship of junior team members on verification BKMs and debug


You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

The candidate must have a minimum Master's degree in Electrical Engineering (EE), or Computer Engineering (CE), or Computer Science CS, and 5+ years of experience, or a PhD degree in Electrical Engineering (EE), or Computer Engineering (CE), or Computer Science in the following experience:

  • Work experience with System Verilog or OVM or UVM or Object-Oriented Programming (OOP)

  • Extensive experience with architecting verification environments and components (random test generators, scoreboards, BFM's, coverage, etc.)

  • Strong understanding of logic design and micro-architecture fundamentals

  • Must demonstrate strong initiative, teamwork, planning, and communication abilities due to deliverables impacting multiple projects and stakeholders.

Preferred Qualifications:

  • Knowledge of standard bus protocols like PCI or IOSF or AHB

  • Knowledge of C/C++ or Perl scripting

Inside this Business Group

In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intels products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moores Law and groundbreaking innovations.  DEG is Intels engineering group, supplying silicon to business units as well as other engineering teams.  As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.

Other Locations

US, California, Folsom

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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Pre-Si Validation Engineer

Santa Clara, CA 95050

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