Physical Design Methodology Engineer - STA

Intel
San Jose, CA 95113
  • Job Code
    JR0163774
  • Jobs Rated
    19th
Job Description

In this position you will be part of a world class Ethernet IP & SOC design team responsible for the design and development of the Ethernet Controllers and Networking Processing of the Network Division Silicon Engineering team. This is a great opportunity to join a talented team and will include lots of product innovation on cutting edge technologies.

Responsibilities for this position include:

  • Defining the STA methodology, generating and validating STA constraints
  • Defining and implementing timing derates/margins/uncertainties, writing timing constraints for IPs like SerDes/DDR/GIOs
  • Define in STA methodologies for FC timing verification for multi mode , multi voltage SoC
  • Responsibility might also include running timing and generating ECOs for timing fixes, assisting junior engineers on timing convergence by finding solutions to critical timing paths, as well as including generation of IO timing constraints
  • Thorough understanding of STA flows/tools like Primetime/Tempus, tools to check and validate timing constraints


Qualifications

Minimum Qualifications

  • Bachelor's degree in Electrical, Electronics or Computer Engineering or other related field of study with 6+ years of experience in physical design
  • 5+ years of experience in physical design/STA methodology in advanced process nodes

Preferred Qualifications

  • 2+ years of experience in circuit design

Inside this Business Group

The Data Center Group (DCG) is at the heart of Intels transformation from a PC company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologiesspanning software, processors, storage, I/O, and networking solutionsthat fuel cloud, communications, enterprise, and government data centers around the world.



Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Jobs Rated Reports for Physicist

Before you go...

Our free job seeker tools include alerts for new jobs, saving your favorites, optimized job matching, and more! Just enter your email below.

Share this job:

Physical Design Methodology Engineer - STA

Intel
San Jose, CA 95113

Join us to start saving your Favorite Jobs!

Sign In Create Account
Physicist
19th2019 - Physicist
Overall Rating: 19/199
Median Salary: $117,220

Work Environment
Very Good
44/220
Stress
Low
78/220
Growth
Good
60/220