Physical Design Engineer

Intel
Santa Clara, CA 95050
  • Job Code
    JR0191366
Job Description

Come and join us at Intel. In this role, you will be part of Intel's Barefoot Division physical design team working on innovative programmable switch ASIC roadmap. You will engage with Architecture, DFT, and packaging to arrive at optimal chip planning early in the design cycle. You will be part of our physical design team working closely with cluster and partition leads to comprehend design challenges and arrive at optimal floorplans. You will play a critical role in die size estimation and evaluating STA tools, timing analysis methods, and flows. Your work will involve meticulous planning of various aspects of floor planning for optimal data flow for high pin densities and to facilitate high confidence timing closure and routability. With your broad understanding of physical design, you will play a critical role in identifying and solving a multitude of design issues at partition/cluster and full chip.

This position is not eligible for Intel immigration sponsorship.


Qualifications

Education Requirements
BS in Electrical or Computer Engineering or related field plus 5 years of semiconductor industry experience.

Minimum Requirements

  • 3+ years in physical design and experience on block closure
  • 3+ years of experience in floor planning and global timing verification, and Physical Design Verification Flows
  • 1+ years of experience  STA (Static Timing analysis) and developing guard bands for desired yield and performance.
  • 2+ years of experience in floor planning tools such as Synopsys ICC2 or Cadence Innovus
  • 1+ years of experience working on advanced process nodes such as 7nm and below.
  • 2+ years of experience with SoC issues such as multiple voltages and clock domains, ESD strategies, mixed-signal block integration

Preferred Qualifications

  • 4+ years of experience in advanced package technologies
  • 3+ years of experience Hierarchical design approach, top-down design, budgeting, timing, and physical convergence
  • 3+ years of experience Integrating IP from both internal and external vendors and to specify and drive IP requirements in the physical domain
  • 3+ years of experience with large SoC designs with power/performance upwards of 1GHz and die size challenges.
  • 1+ years of experience in various process-related design issues, including Design for Yield and Manufacturability, multi-Vt strategies, and thermal management

Inside this Business Group

The Network & Edge Group brings together our network connectivity and edge into a business unit chartered to drive technology end to end product leadership. It's leadership Ethernet, Switch, IPU, Photonics, Network and Edge portfolio is comprised of leadership products critically important to our customers.



Other Locations

US, California, San Diego;US, California, San Jose


Intel Corporation will require all new U.S. employees to be fully-vaccinated for Covid-19 as a condition of hire unless they have an approved accommodation in place under applicable law. Newly-hired employees will be required to provide proof of vaccination prior to their start date.



Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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Physical Design Engineer

Intel
Santa Clara, CA 95050

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