Physical Design Engineer

Intel
Santa Clara, CA 95050
  • Job Code
    JR0190781
Job Description

Job Description

The world is transforming and so is Intel!  Here at Intel, we believe the world needs technology that can enrich the lives of every person on earth. We work every single day to design and manufacture silicon products that empower peoples digital lives. Do you love to solve technical challenges that no one has solved yet? Do you enjoy working with cross functional teams to deliver solutions for products that impact customers lives? If so, Come join us to do something wonderful!

In this position, you will participate in standard cell layout development and delivery for corporate standard cell libraries for use in designs of Intels SoCs microprocessors, etc

Responsibilities include but are not limited to:

  • Understanding of standard cell architecture Design of standard cell layouts Optimization of standard cell layouts considering area, performance, reliability tradeoffs Verification of layouts for design and architecture rules Understanding and implementation of DFM and ESD guidelines Understanding of RC delay electro migration self-heating and coupling capacitance
  • Ability to recognize failure prone layout structures and produce robust layouts Equivalence verification of layouts with respect to schematics Development of automation for library design quality checking and reliability verification Release verification and handoff.
  • Candidate must possess excellent written and verbal communication skills, strong team orientation, and ability to work in a flexible manner realigning to latest schedule requirement as needed


Qualifications

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You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Candidate must have a Bachelor's degree in Electronics Engineering with 4+ years of experience -OR- AA degree with 8+ years of experience in:

  • Designing and optimizing VLSI layout at the cell and or block level on different silicon process technologies

Preferred Qualifications:

  • Knowledge of CAD layout tools eg Cadence Virtuoso Synopsys Custom Compiler any other industry-standard layout development tool
  • Experience using design rule checkers and layout verification tools
  • Knowledge of additional layout automation capabilities eg process shift
  • Knowledge of scripting languages TCL Perl Skill Python for design automation

Inside this Business Group

IP Engineering Group's (IPG) vision Build IPs that power Intel's leadership products and power our customer's silicon. We want to attract & retain talent who get joy in building high quality IP and share our core belief that IP is fundamental to transforming Intel's silicon design process. IPG's guiding principles will be ensuring Quality (Zero Bugs), Customer Obsession (Delight our Customers) and structured Problem Solving. We are a fearless organization transforming IP development.



Other Locations

US, California, Folsom;US, Oregon, Hillsboro


Intel Corporation will require all new U.S. employees to be fully-vaccinated for Covid-19 as a condition of hire unless they have an approved accommodation in place under applicable law. Newly-hired employees will be required to provide proof of vaccination prior to their start date.



Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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Physical Design Engineer

Intel
Santa Clara, CA 95050

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