Physical Design Engineer

Intel
Santa Clara, CA 95050
  • Job Code
    JR0188441
Job Description

The Xeon & Networking Engineering Group (XNE) is focused on developing and delivering networking and 5G products for the data center roadmap.

This role involves a blend of physical design methodology development and consulting in physical implementation. This role also involves supporting product/methodology development in new technology nodes.

In this role responsibilities include, although not limited to:

  • Contribute to physical design methodology development covering early technology exploration, place and route, FILL/DRC/LVS, and chip finishing
  • Work with internal design implementation teams and external customers in physical design and design closure aspects
  • Define, develop and support IP physical abstraction methodology, tools, and flows
  • Support development and refinement of foundry technology files and associated chip finishing utility scripts
  • Work with 3rd party EDA vendors, CAD tool developers, and internal IP teams to resolve issues and drive improvements in vendor tools / IP deliverables.
  • Support SoC and IP design teams in implementing new techniques.
  • Oversee definition, design, verification, and documentation for SoC (System on a Chip) development.
  • Determine architecture design, logic design, and system simulation.
  • Define module interfaces/formats for simulation.
  • Perform Logic design for integration of cell libraries, functional units and subsystems into SoC full chip designs, Register Transfer Level coding, and simulation for SoCs.
  • Contribute to the development of multidimensional designs involving the layout of complex integrated circuits.
  • Perform all aspects of the SoC design flow from high-level design to synthesis, place and route, timing and power to create a design database that is ready for manufacturing.
  • Analyze equipment to establish operation infrastructure, conducts experimental tests, and evaluates results.
  • May also review vendor capability to support development.

In addition to the below listed qualifications the candidate should have:

  • Effective presentation and communication skills (written and oral).
  • Strong problem-solving skills and willing to think outside the box.
  • Ability to work/lead effectively in cross-functional teams / multiple geographies and mentor junior engineers when needed.


Qualifications

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

The candidate must have a Master of Science in Electrical Engineering or equivalent with 4+ years of experience in:

  • Understanding of ASIC design flow with a focus on physical design and timing closure.

Preferred Qualifications:

  • Experience in Prior methodology development, EDA vendor/Foundry interaction or exposure to technology nodes 5nm and below.

Inside this Business Group

Xeon and Networking Engineering (XNE) focuses on the development and integration of XEON and Networking SOC's and critical IP's sustain Intels Xeon and 5G networking roadmap.


Intel Corporation will require all new U.S. employees to be fully-vaccinated for Covid-19 as a condition of hire unless they have an approved accommodation in place under applicable law. Newly-hired employees will be required to provide proof of vaccination prior to their start date.



Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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Physical Design Engineer

Intel
Santa Clara, CA 95050

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