Physical Design Engineer

Intel
Santa Clara, CA 95050
  • Job Code
    JR0169270
Job Description

In this role you will be part of Intel's Barefoot Division under the Connectivity Group working on exciting programmable switch ASIC roadmap. You will engage with Architecture, DFT and packaging to arrive at optimal chip planning early in the design cycle. You will be part of our physical design team working closely with cluster and partition leads to comprehend design challenges and arrive at optimal floorplans. You will play a critical role in die size estimation and in evaluating floorplan tools, methods and flows. Your work will involve meticulous planning of various aspects of floor planning for optimal data flow for high pin densities and to facilitate high confidence timing closure and routability. With your broad understanding of physical design you will play a critical role in identifying and solving multitude of design issues at partition/cluster and full chip.


Qualifications

Minimum Qualifications


BS in Electrical or Computer Engineering or similar degree with 4+ years of experience.

  • 3+ years in physical design and experience on block closure
  • 2+ years of experience in floor planning and global timing verification and Physical Design Verification Flows
  • 2+ years of experience in floor planning tools such as ICC2 DP or Cadence Encounter
  • 2+ years of experience with SoC issues such as multiple voltage and clock domains, ESD strategies, mixed signal block integration

Preferred Qualifications

  • 3+ years of experience in  advanced package technologies
  • 3+ years of experience Hierarchical design approach, top-down design, budgeting, timing and physical convergence
  • 3+ years of experience Integrating IP from both internal and external vendors and to specify and drive IP requirements in the physical domain
  • 3+ years of Experience with large SoC designs with power/performance upwards of 1GHz and die size challenges.
  • 1+ years of experience in various process related design issues including Design for Yield and Manufacturability, multi Vt strategies and thermal Mgt.

Inside this Business Group

The Data Center Group (DCG) is at the heart of Intels transformation from a PC company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologiesspanning software, processors, storage, I/O, and networking solutionsthat fuel cloud, communications, enterprise, and government data centers around the world.



Other Locations

US, Arizona, Phoenix;US, North Carolina, Raleigh



Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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Physical Design Engineer

Intel
Santa Clara, CA 95050

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