Physical Design Engineer

San Jose, CA 95113
  • Job Code
Job Description

In this position you will be part of a world class Ethernet IP & SOC design team responsible for the design and development of the Ethernet Controllers and Networking Processing of the Network Division Silicon Engineering team.  You will perform all aspects of the physical design flow from engaging with design team through synthesis, place and route, timing analysis and power reduction.  This is a great opportunity to join a talented team and will include lots of product innovation on cutting edge technologies.

Responsibilities will include but not limited to:

  • Drive technical activities during all phases of physical design execution
  • Work extensively with SoC and RTL teams to help optimize/converge the designs to achieve the best Power, Performance, and Area (PPA).
  • Ensure cross geos and cross functional teams communication
  • Sub-Chip level and block-level floor planning
  • Power supply and power grid planning and analysis,
  • Logic synthesis of design blocks,
  • Formal Equivalence Verification (FEV),
  • Clocking network planning and analysis,
  • Auto Place-and-Route (APR) using Synopsys ICC tools / Cadence Innovus tools,
  • Timing signoff and timing ECO using Synopsys Prime Time,
  • Physical verification - Layout vs. Schematic (LVS), Design Rule Checks (DRC), Electrical Rule Checks (ERC)
  • Eager to improve, influence tools, flows and overall RTL to GDS physical design methodology with data-drive approach.

In addition to the qualifications listed below the ideal candidate will also have:

  • Excellent analytical and problem-solving skills,
  • Strong verbal/written communication skills,
  • Effective team player with continuous learning mindset,
  • Willingness to balance multiple tasks,
  • Willingness to work in a fast-paced environment and have as much fun and growth as possible in the process.
  • The group is looking for someone who can balance innovation with flawless execution.



You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications

Candidate must have a Bachelor's degree in Computer science/Electrical or Computer Engineering with 4 plus years of experience -OR- a Master's degree in Computer science/Electrical or Computer Engineering with 3 plus years of experience OR- a PhD in Computer science/Electrical or Computer Engineering in addition to the following:

  • 3 plus years of experience executing on complex network SoC/ASICs.
  • 3 plus years Scripting using a programming language such as Perl, TCL, or Python

Preferred Qualifications

  • Experience working on advanced process nodes such 7nm and below
  • Deep understanding of semiconductor device physics
  • Understanding of Physical Design and verification Tools, Flows and Methods
  • Expert user of physical design tools such as DC (Design Compiler), ICC2/Innovus, PrimeTime, etc.
  • Good experience with Redhawk for signal EM and IRdrop analysis

Inside this Business Group

The Data Center Group (DCG) is at the heart of Intels transformation from a PC company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologiesspanning software, processors, storage, I/O, and networking solutionsthat fuel cloud, communications, enterprise, and government data centers around the world.

Other Locations

US, Arizona, Phoenix

Intel Corporation will require all new U.S. employees to be fully-vaccinated for Covid-19 as a condition of hire unless they have an approved accommodation in place under applicable law. Newly-hired employees will be required to provide proof of vaccination prior to their start date.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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Physical Design Engineer

San Jose, CA 95113

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