Physical Design Engineer

Phoenix, AZ 85003
  • Job Code
Job Description

Join the Intel IPG Physical Design team! Our team delivers custom layout for various mixed-signal IP technologies which are used by many products across Intel's spectrum of products, including client CPUs, Server CPUs and other products. Our global physical design team focuses on sensitive analog components of memory, high speed IO, PLLs.

Responsibilities will include but are not limited to:

  • Creates bottoms up elements of chip design including but not limited to FET, cell, and block level custom layouts, floor plans, abstract view generation, RC extraction and schematic to layout verification
  • Debug using phases of physical design development including parasitic extraction, static timing, wire load models, clock generation, customer polygon editing, auto place and route algorithms, floor planning, full chip assembly, packaging, and verification.
  • Troubleshoots a wide variety up to and including difficult design issues and applied proactive intervention
  • Schedules, staffs, executes and verifies complex chips development and execution of project methodologies and/or flow developments.


  • Ability to confidently represent teams in key project meetings and events
  • In addition to the qualifications listed below, the ideal candidate will also have good work ethics with an emphasis on teamwork and customer obsession


You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:
The candidate must have a Bachelor's degree in Electrical Engineering (EE), Computer Engineering (CE), or Computer Science (CS) with 3+ years of industry experience -OR- a Master's degree in Electrical Engineering (EE), Computer Engineering (CE) Computer Science CS with 2+ years of industry experience in:

  • Electronic circuit functionality and behaviors
  • Complementary Metal Oxide Semiconductor CMOS and Very Large Scale Integration VLSI component design principles

Preferred Qualifications:

  • Knowledge of CAD layout software

Inside this Business Group

IP Engineering Group's (IPG) vision Build IPs that power Intel's leadership products and power our customer's silicon. We want to attract & retain talent who get joy in building high quality IP and share our core belief that IP is fundamental to transforming Intel's silicon design process. IPG's guiding principles will be ensuring Quality (Zero Bugs), Customer Obsession (Delight our Customers) and structured Problem Solving. We are a fearless organization transforming IP development.

Other Locations

US, California, Folsom

Intel Corporation will require all new U.S. employees to be fully-vaccinated for Covid-19 as a condition of hire unless they have an approved accommodation in place under applicable law. Newly-hired employees will be required to provide proof of vaccination prior to their start date.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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Physical Design Engineer

Phoenix, AZ 85003

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