Physical Design Engineer

Intel
Hillsboro, OR 97123
  • Job Code
    JR0200227
Job Description

Full chip integration team is an integral part of Silicon and Systems prototyping Lab (SSPL) enabling integration and tape out of prototypes. Your work will directly enable stake holders in providing ease of use design methodologies, executing to cutting edge technologies.

As part of Full chip integration team you will join highly motivated team of talented engineers works to aggressive schedules by clearly communicating technical tradeoffs, solving challenging technical problems in backend design and integration, design collateral releases and ensuring successful test chip tapeouts.

As a Physical Design Engineer your responsibilities include, but are not limited to:

  • Creates bottomsup elements of chip design including but not limited to FET, cell, and blocklevel custom layouts, FUBlevel floor plans, abstract view generation, RC extraction and schematic to layout verification and debug using phases of physical design development including parasitic extraction, static timing, wire load models, clock generation, customer polygon editing, autoplace and route algorithms, floor planning, full chip assembly, packaging, and verification.

  • Troubleshoots a wide variety up to and including difficult design issues and applied proactive intervention.

  • Verifies complex chips development and execution of project methodologies and/or flow developments.


Qualifications

You must possess the below minimum qualifications to be considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

  • The Candidate must possess a Master's degree in Electrical Engineering, Computer Engineering or Electrical & Computer Engineering.

  • 4+ years of experience in DRC/LVS Runset and algorithm development. Specific experience with Auto place and route algorithms

  • 3+ years of experience in below areas:
    - DRC/LVS Runset and algorithm development. Specific experience with Auto place and route algorithms.

    - C/C++/Java/Perl programming language.
    - Data Structures, Algorithms and Optimizations.
    - Microprocessor floor planning, FUB integration, layout design rules and schematic/layout comparison debug and correction.
    - Physical layout, verification and be proficient in layout assignments from upper level layout, floor planning and component level layout.
    - Physical Design Verification methodology to debug LVS/DRC issues at both device, block and top levels.

Preferred Qualifications:

  • Firm grasp of programming tools and knowledge in VLSI domain

  • Excellent working ability with circuit design and layout methodologies in a team environment.

  • Capable of sharing tool knowledge and expertise with other physical designers and contribute to a positive team environment through developing and proliferating best known methods

  • A proven experienced lead, driving execution as well as effectiveness process improvements.

Inside this Business Group

Intel Labs is the company's world-class, industry leading research organization, responsible for driving Intel's technology pipeline and creating new opportunities. The mission of Intel Labs is to deliver breakthrough technologies to fuel Intel's growth. This includes identifying and exploring compelling new technologies and high risk opportunities ahead of business unit investment and demonstrating first-to-market technologies and innovative new usages for computing technology. Intel Labs engages the leading thinkers in academia and industry in addition to partnering closely with Intel business units.


Intel Corporation will require all new U.S. employees to be fully-vaccinated for Covid-19 as a condition of hire unless they have an approved accommodation in place under applicable law. Newly-hired employees will be required to provide proof of vaccination prior to their start date.



Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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Physical Design Engineer

Intel
Hillsboro, OR 97123

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