Physical Design Engineer - Clocking Constraints

Intel
Hillsboro, OR 97123
  • Job Code
    JR0185637
Job Description

The world is transforming and so is Intel!  Here at Intel, we believe the world needs technology that can enrich the lives of every person on earth. We work every single day to design and manufacture silicon products that empower peoples digital lives. Do you love to solve technical challenges that no one has solved yet? Do you enjoy working with cross functional teams to deliver solutions for products that impact customers lives? If so, Come join us to do something wonderful!

Join a IP team which is providing key Intel IP for Xeon products. We are a front-end RTL team looking for an experienced physical engineer to contribute to the constraint generation. Exciting environment to help define the methodology behind an IP going into multiple process nodes, multiple SoCs. Specific tasks related to RTL qualification before hand-off to physical design team.

In addition to the qualifications listed below the ideal candidate will also have:

  • Excellent analytical and problem-solving skills
  • Strong verbal/written communication skills
  • Effective team player with continuous learning mindset
  • Willingness to balance multiple tasks
  • Willingness to work in a fast-paced environment and have as much fun and growth as possible in the process


Qualifications

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

Candidate must have a Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field with 4+ years of experience - OR - Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field with 3+ years of experience in:

  • Physical design and experience on block closure.
  • Generating constraints which includes I/O timing, clocking, and exceptions.
  • Physical flows which includes synthesis, DFT insertion, floor planning and global timing verification and Physical Design Verification Flows.
  • Design or Fusion compiler experience required.

Preferred Qualifications:

  • Some experience with methodology desired.
  • Excel, and scripting such as Python/tcl/Perl.
  • Exposure to RTL logic coding

Inside this Business Group

IP Engineering Group's (IPG) vision Build IPs that power Intel's leadership products and power our customer's silicon. We want to attract & retain talent who get joy in building high quality IP and share our core belief that IP is fundamental to transforming Intel's silicon design process. IPG's guiding principles will be ensuring Quality (Zero Bugs), Customer Obsession (Delight our Customers) and structured Problem Solving. We are a fearless organization transforming IP development.



Other Locations

US, Arizona, Phoenix;US, California, Santa Clara



Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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Physical Design Engineer - Clocking Constraints

Intel
Hillsboro, OR 97123

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