Physical Design Engineer

Intel
Allentown, PA 18101
  • Job Code
    JR0171353
Job Description

As part of the Xeon team in Allentown you will be working with SoC physical design flow from synthesis thru place and route, timing and power analysis and verification to create a design database that is ready for manufacturing.

In this role you will:

  • Lead and mentor junior engineers in specific physical design domains(Tool Flow Methodology), DFT (Design For test) to optimize for convergence
  • Deliver high quality structural design database on schedule
  • Perform floor planning and routing studies and implement logic synthesis and APR for SoC blocks, sections and full chip timing analysis
  • Evaluate low power techniques and power reduction opportunities
  • Perform clock distribution design and analysis, power integrity and reliability analysis and verification, as well as functional equivalence verification
  • Drive technical activities during all phases of execution
  • Review and direct technical engagement with contingent workforce
  • Guide and collaborate with partner domains like Logic TFM

 

In addition to these qualifications the ideal candidate will:

  • Be willing to work independently and at different levels of abstraction
  • Have excellent written and verbal communication skills
  • Effectively collaborate with teams, customers & vendors
  • Strong analytical and problem solving skills
  • Willing to work effectively in a multi-site  results driven team to achieve high quality results


Qualifications

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:


The candidate must have a Bachelors degree in Electrical / Computer Engineering or related computing disciple and 4+ years of experience OR a Masters degree in Electrical / Computer Engineering or related computing disciple and 3+ years of experience in:

  • SoC IP Physical Design
  • Design Closure
  • Floor planning and routing
  • Clock Design & Implementation
  • Performance Verification (Timing Closure etc.)
  • Layout Verification (DRC/LVS etc.)
  • Reliability Verification (Power Analysis etc.)
  • Experience with Industry standard EDA tools, Synopsys preferred

Inside this Business Group

Xeon and Networking Engineering (XNE) focuses on the development and integration of XEON and Networking SOC's and critical IP's sustain Intels Xeon and 5G networking roadmap.



Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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Physical Design Engineer

Intel
Allentown, PA 18101

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