Physical Design Automation Engineer

Santa Clara, CA 95050
  • Job Code
Job Description

Join Intel-and engineer the future.

Intel is in the midst of an exciting transformation, with a vision to create and extend computing technology to connect and enrich the lives of every person on Earth. So join us-and help us create the next generation of technologies that will shape the future for decades to come. Intel IP Engineering Group invites you to be part of a senior team dedicated to providing cutting edge backend design tools, flows and methodology for ground-breaking high-performance IPs. This is a unique chance to join an experienced team, as we continue transforming ourselves into the IP supplier of choice for flagship Intel SoCs. Current efforts include design innovations to achieve best in class performance across a broad scope of IPs and process technologies, as well as defining and driving tools and methodology advancement across the IP execution teams.

Your responsibilities will include, but not be limited to:

  • Develop, Deploy and Support design and verification tools for IPG Physical and Structural Design Engineers covering various areas such as:
  • Design Infrastructure/Environment,
  • Logic Synthesis and Auto-Place and Route,
  • Performance Verification,
  • Extraction,
  • Collateral Packaging and Release and others across multiple technology nodes (both Internal/External)Work closely with IP design teams to lead evaluations, benchmarking and testing of new tools for identifying efficiency improvements.
  • Partner with Tool Vendors closely to coordinate releases, debug complex issues and identifying and communicate unique IPG design team needs or gaps with the current tools.
  • In addition to supporting Tool flows, you will provide and maintain documentation, BKM's sharing, and training to IPG design engineers to enable best in class Design Tool capabilities for IPG.

In addition to the qualifications listed below the ideal candidate will also have:

  • Excellent analytical and problem-solving skills
  • Strong verbal/written communication skills
  • Effective team player with continuous learning mindset
  • Willingness to balance multiple tasks
  • Willingness to work in a fast-paced environment and have as much fun and growth as possible in the process


You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:
The candidate must have a Bachelor's degree in Electrical/Computer Engineering or other related field of study and 4+ years of experience in - OR - a Masterr's degree in Electrical/Computer Engineering or other related field of study and 3+ years of experience in

  • Solid understanding of Physical Design and verification TFM
  • Experience in using Static Timing Analysis Flows and Tools such as Primetime, or Industry standard Synthesis and Place and Route tools such as Synopsys Design/Fusion Compiler.
  • Scripting languages such as Perl, Python, TCL, etc..

Preferred Qualifications:

  • Experience in utilizing or supporting additional design implementation or verification tool flows in one or more of the following areas: Synthesis and Place and Route Tools, Power Optimization, Static Timing Analysis, Extraction, Formal Verification, Layout Verification, Reliability Verification.
  • Experience with External process nodes.

Inside this Business Group

IP Engineering Group's (IPG) vision Build IPs that power Intel's leadership products and power our customer's silicon. We want to attract & retain talent who get joy in building high quality IP and share our core belief that IP is fundamental to transforming Intel's silicon design process. IPG's guiding principles will be ensuring Quality (Zero Bugs), Customer Obsession (Delight our Customers) and structured Problem Solving. We are a fearless organization transforming IP development.

Other Locations

US, Arizona, Phoenix;US, California, Folsom;US, Colorado, Fort Collins;US, Oregon, Portland

Intel Corporation will require all new U.S. employees to be fully-vaccinated for Covid-19 as a condition of hire unless they have an approved accommodation in place under applicable law. Newly-hired employees will be required to provide proof of vaccination prior to their start date.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Annual Salary Range for jobs which could be performed in US, Colorado:

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, and benefit programs. Find more information about our Amazing Benefits here

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Physical Design Automation Engineer

Santa Clara, CA 95050

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