Memory IP Design Engineer

Intel
Hillsboro, OR 97123
  • Job Code
    JR0179671
Job Description

The High Density Memory Group within Technology Development is looking for a motivated Memory IP Design Engineer. The near term responsibility of the role is to do the IP signoff and development of non-volatile and dynamic memories. But long term, you will be part of the state of the art memory technology development team working with semiconductor technologists, designers, engineers and architects. It is a unique opportunity to work on several differentiating technology which will spearhead Intel's path as IDM2.0 and make us standout in all product segments including client, servers, FPGA.

You will be responsible for:

  • Perform rigorous IP QA checks for bug free full-chip integration.
  • Static timing analysis and communicating high sanctity .LIB files.
  • Communicating and educating the IP functional and performance features to next level teams.
  • Running front end and back end flows for complete verification of the memory HIP. Do RTL coding and create testbenches for validation as needed.
  • Overseeing post-silicon debug and facilitating the IP certification by closely working with full chip teams and test engineers.
  • Interacting with external/internal customers to oversee full-chip/SOC FEBE, and resolve bugs and clarifications.


Qualifications

Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:
BS Degree in EE with 3+ years of semiconductor experience OR MS Degree in EE ith 2+ years semiconductor experience in the following areas:

  • Custom VLSI circuit design
  • Layout Spice simulations
  • Post-layout extraction


Preferred Qualifications:

  • Static timing analysis and IP signoff knowledge
  • Basic scripting experience
  • RTL to GDS and state of the art APR flows.
  • Knowledge of IP collaterals such as .LIB
  • Experience with quality checks such as Lintra, CDC, Spyglass

#designenablement
@designenablemnt
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Inside this Business Group

As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support.  Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moores Law to bring smart, connected devices to every person on Earth.



Other Locations

US, California, Santa Clara


Intel Corporation will require all new U.S. employees to be fully-vaccinated for Covid-19 as a condition of hire unless they have an approved accommodation in place under applicable law. Newly-hired employees will be required to provide proof of vaccination prior to their start date.



Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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Memory IP Design Engineer

Intel
Hillsboro, OR 97123

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