MBIST TFM Engineer

Intel
Santa Clara, CA 95050
  • Job Code
    JR0185444
Job Description

As a EDA Tools and Methodology engineer, you will work to develop test automation solutions for logic and memory Design-for-Test (DFT) insertion and verification, array test algorithms and test development, logic test content generation e.g. Automatic Test Pattern Generation (ATPG) and modular test content reuse. You will architect, develop and deploy CAD capabilities to address problems in this space and adapt off-the-shelf capabilities where available to build solutions. You will collaborate with an interdisciplinary team spanning chip design, product development and process technology development.

In addition to the qualifications listed below, the ideal candidate will also have:

  • Analytical skills for problem abstraction
  • Skills to apply scientific methods to investigate problems and to reduce ambiguity in making technical decisions


Qualifications

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

The candidate must possess a Bachelor's degree in Electrical/Computer Engineering or Computer Science or a related field with 3+ years experience -OR- a Master's degree in Electrical/Computer Engineering or Computer Science or a related field with 2+ years experience -OR- a Ph.D. in Electrical/Computer Engineering or Computer Science, or a related field with a thesis in the area of DFT, test CAD or formal verification and experience in the following:

  • Logic and memory design principles, VLSI design flow and VLSI CAD algorithms
  • Tool, flows and methodology development for DFT insertion or test generation needs
  • Programming skills with one or more of the high level languages e.g. TCL/Perl etc.

Preferred Qualifications:

Experience in:

  • Programming with either C++ or C
  • Computer science, including algorithms and data structures
  • Standard software engineering practices for version control, configuration management, debugging and validation

Inside this Business Group

In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intels products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moores Law and groundbreaking innovations.  DEG is Intels engineering group, supplying silicon to business units as well as other engineering teams.  As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.



Other Locations

US, California, Folsom;US, Colorado, Fort Collins;US, Oregon, Hillsboro



Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Annual Salary Range for jobs which could be performed in US, Colorado:
$95,360.00-$143,140.00


Benefits:
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, and benefit programs. Find more information about our Amazing Benefits here

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MBIST TFM Engineer

Intel
Santa Clara, CA 95050

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