Mask Designer

Phoenix, AZ 85003
  • Job Code
Job Description

Assembly and Test Technology Development (ATTD) Mask Designer develops and prepare multidimensional layouts for assembly test chips.

  • Responsibilities may be directed at a specific point in the design cycle, or vary as the project progresses through the design stage
  • Assignments are somewhat complex in nature
  • Work performed within generally defined parameters
  • Judgment is required in resolving moderately complex problems
  • Normally receives general instructions on routine work, detailed instructions on new work

Roles and Responsibilities:

  • Performs as a proficient technical individual contributor or specialist on complex layout/leadership assignments
  • Leadership responsibilities could include complex block layout, small to medium scope sections, small to medium scope projects, methodology development, etc.
  • Given project conditions and constraints, develops detailed task lists, resource forecasts, and both short- and long-range schedules for sections and projects
  • Coordinate, facilitate, and monitor the daily activities of a small to medium group of support resources within their block, section, or project team
  • Prioritizes workload of parallel tasks and responsibilities with minimal supervision
  • Design Rule and DRC Debug skills.
  • Manages daily operations within their assignments, showing appropriate consideration for established project objectives and standard project methodologies with minimal supervision
  • Develop the skills of less experienced layout designers through training, coaching, and mentoring
  • Proactively addresses and communicates issues impacting productivity and works to resolve roadblocks


You must possess the below minimum qualifications to be initially considered for this position.

Preferred qualifications are in addition to the minimum qualifications and are considered a plus factor in identifying top candidates.

Minimum Qualification

  • Possess an associate's degree in Electronics or related field with 5+ years of direct layout experience in Semiconductor Process Node Technologies

Preferred Qualifications

5+ years of experience in one or more of the following:

  • Cadence Virtuoso, Design Rule and DRC Debug skills (plus)
  • Industry-based verification tools including Calibre DRC, LVS (plus)
  • Block, section/chip level ownership, including forecasting, scheduling, and execution (plus)
  • Just-in-time scripts in Skill, Tcl, or similar scripting languages (automate design tasks/improve efficiency)

Inside this Business Group

As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support.  Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moores Law to bring smart, connected devices to every person on Earth.

Other Locations

US, Oregon, Hillsboro

Intel Corporation will require all new U.S. employees to be fully-vaccinated for Covid-19 as a condition of hire unless they have an approved accommodation in place under applicable law. Newly-hired employees will be required to provide proof of vaccination prior to their start date.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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Mask Designer

Phoenix, AZ 85003

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