Logic Design Engineer

San Jose, CA 95113
  • Job Code
Job Description

Come and join us. Intel is seeking highly qualified candidates to join the BXD (Barefoot Switching Division) in our Network and Edge Group (NEX) as a Logic Design Engineer. We're part of the Connectivity Group (CG) in Intel's NEX, and are looking for motivated, passionate and talented design engineers to join our Networking Applications development team for programmable high-speed switching ASICs. We're a strong, vibrant, cross-site team that helps drive Intel's programmable switching technology and products to position Tofino. as the switching platform of choice for Cloud and Data Center network deployments.

In this role, as part of the Chip team, you will need to be passionate about developing high-performance programmable switching ASICs. You will have an excellent opportunity to define and design the next generation Intel Programmable Ethernet Switch.

Responsibilities will include, but are not limited to:

  • Define and write architecture and microarchitecture specification.
  • Design those RTL functionalities using System Verilog associated with assertions and cover point, run lint tool and reset/clock domain crossing tool, write synthesis constraint file and analyze synthesis results.
  • Integrate both internal and external high-performance IP such as PCI-Express, Ethernet Controller, high-end Serdes, high-performance embedded CPUs and their peripherals.
  • Work closely with verification engineer to debug those functionalities.
  • Work closely with DFx and Physical Design Engineer for floor planning activity, synthesis and timing analysis.
  • Participate in design and code-reviews of other design engineer.
  • Debugging regression failures as well as issues reported by customers on the field and coming up with practical solutions and fixes.

The ideal candidate will have the following skills in addition to the qualifications listed below:

  • Must be a team player, with demonstrated skill to technically influence others.
  • Strong problem-solving skills.
  • Excellent verbal and written communication skills.

In this position you will gain invaluable experience which will allow growth and expanded opportunities within this business group as well as future possible opportunities with other business groups within Intel.

The Connectivity Group (CG) drives new products technologies in the areas of Programmable switching devices, and Smart NICs, Silicon Photonics for data center fabrics. The BXD team is driven by deep engineering skills and a love of cutting-edge projects. We are building the world's fastest switches that are also fully programmable, ensuring the network can adapt to meet the emerging needs of applications and empower users to write solutions rapidly, and to innovate broadly. We believe that when the network is fully programmable-that is, both the control plane and data plane are under the control of the end user- the networking industry will enjoy the same innovative explosion as we have seen in software.


You must possess the below minimum qualifications to be initially considered for this position Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Education Requirement:

  • Bachelor's degree in Computer Science Electrical Engineering or related field and 4+ years of industry work experience or
  • Master's degree in Computer Science Electrical Engineering or related field and 3+ years of industry work experience or
  • PhD in Computer Science Electrical Engineering or related field and 1+ years of industry work experience

Minimum Required Qualifications:

  • 4+ years of experience in RTL design using System Verilog.
  • 2+ years of experience in complex IP integration and debugging them.
  • 2+ years of experience in embedded CPU sub-system integration, on chip bus architecture such as network-on-chip, AMBA4 AXI/APB protocol, DMA architecture and/or or high speed Serial Link protocol such as PCI-Express, CXL and/or Ethernet.
  • 1+ years of experience in scripting languages such as Python/ Perl.

Additional Preferred Qualifications:

  • 1+ years of experience with integration/design of system boot, analog IP integration such as PLL and PVT sensor, low speed interface such as I2C/MDIO/JTAG/SPI.
  • 1+ years of experience in Ethernet Auto-Negotiation and Link Training or PCI-Express Rx Equalization Training.
  • 1+ years of experience in understanding of DFx functionalities such as BIST, Scan, ACJTAG, iJTAG.

Inside this Business Group

The Data Center Group (DCG) is at the heart of Intels transformation from a PC company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologiesspanning software, processors, storage, I/O, and networking solutionsthat fuel cloud, communications, enterprise, and government data centers around the world.

Intel Corporation will require all new U.S. employees to be fully-vaccinated for Covid-19 as a condition of hire unless they have an approved accommodation in place under applicable law. Newly-hired employees will be required to provide proof of vaccination prior to their start date.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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Logic Design Engineer

San Jose, CA 95113

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