Logic Design Engineer

San Jose, CA 95113
  • Job Code
Job Description

Oversees definition, design, verification, and documentation for SoC (System on a Chip) development. Determines architecture design, logic design, and system simulation. Defines module interfaces/formats for simulation. Performs Logic design for integration of cell libraries, functional units and subsystems into SoC full chip designs, Register Transfer Level coding, and simulation for SoCs. Contributes to the development of multidimensional designs involving the layout of complex integrated circuits. Performs all aspects of the SoC design flow from highlevel design to synthesis, place and route, timing and power to create a design database that is ready for manufacturing. Analyzes equipment to establish operation infrastructure, conducts experimental tests, and evaluates results. May also review vendor capability to support development.


You must possess the below minimum qualifications to be initially considered for this position Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Education Requirements:

  • Bachelors degree in Computer Science Electrical Engineering or related field plus 4 years of industry work experience or

  • Masters degree in Computer Science Electrical Engineering or related field plus 3 years of industry work experience or

  • PhD in Computer Science Electrical Engineering or related field plus 1 years of industry work experience

Minimum Required Qualifications:

  • 4 + years of experience in RTL design using System Verilog

  • 2 + years of experience in complex IP integration and debugging them

  • 2 + years of experience in embedded CPU sub-system integration, on chip bus architecture such as network-on-chip, AMBA4 AXI/APB protocol, DMA architecture and/or or high speed Serial Link protocol such as PCI-Express, CXL and/or Ethernet

  • 1 + year of experience in scripting languages such as Python/ Perl

Additional Preferred Qualifications:

  • 1 + year of experience with integration/design of system boot, analog IP integration such as PLL and PVT sensor, low speed interface such as I2C/MDIO/JTAG/SPI

  • 1 + year of experience in Ethernet Auto-Negotiation and Link Training or PCI-Express Rx Equalization Training

  • 1 + year of experience in understanding of DFx functionalities such as BIST, Scan, ACJTAG, iJTAG

Inside this Business Group

The Data Center Group (DCG) is at the heart of Intels transformation from a PC company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologiesspanning software, processors, storage, I/O, and networking solutionsthat fuel cloud, communications, enterprise, and government data centers around the world.

Other Locations

US, Oregon, Hillsboro

Intel Corporation will require all new U.S. employees to be fully-vaccinated for Covid-19 as a condition of hire unless they have an approved accommodation in place under applicable law. Newly-hired employees will be required to provide proof of vaccination prior to their start date.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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Logic Design Engineer

San Jose, CA 95113

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