Layout Engineer

Intel
Hillsboro, OR 97123
  • Job Code
    JR0180167
Job Description

This position is within the Design Enablement (DE) organization of Technology Development (TD). At Intel, Design Enablement is one of the key pillars enabling Intel to deliver winning products in the marketplace. Your work will directly enable design teams to get to market faster with leadership products on cutting-edge technologies.

You will be part of the Intel Advanced Design Organization (AD) within Design Enablement (DE), focused on pathfinding and development of advanced memory and circuit technology to enable best-in-class memory collateral and product design across all generations of Intel process technology. Our AD organization delivers critical technology and design collaterals to enable future product designs, develops the 1st chips for all new Intel technology nodes, ensure process and design enablement are robust for high volume product manufacturing.

In this position, you will be responsible for the physical layout implementation of standard cells, digital/custom circuits, or mixed-signal circuits. You will work closely with experienced mask designers and design engineers on next-generation process nodes for test-chip and design technology co-optimization projects.

The Candidate should exhibit the following behavioral traits:

  • Self-driven with the ability to work in cross-functional teams
  • Written and verbal communications skills
  • Enjoy solving complex spatial puzzles.


Qualifications

Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

Possess a Bachelors degree in Electrical Engineer, Electronics Engineer or Computer Engineering

                                                                 

2+ years semiconductor industry experience in the below area:

  • Cadence Virtuoso or Synopsys Custom Compiler
  • Custom IC layout techniques Digital or Analog
  • LVS, DRC, DFM, and ERC using physical verification tools such as ICV, Calibre
  • Scripting Languages Perl, TCL, Python, or SKILL

 

Preferred Qualifications:

  • Leading node process technology (such as 10nm/7nm/5nm ...)
  • Optimization techniques for IR drop, RC delay, EM/SH, coupling capacitance
  • System-on-chip design flows and APR tools

 

#designenablement
@designenablemnt
#LI-JR1

Inside this Business Group

As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support.  Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moores Law to bring smart, connected devices to every person on Earth.



Other Locations

US, Arizona, Phoenix



Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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Layout Engineer

Intel
Hillsboro, OR 97123

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