IP Validation Lead Engineer

Santa Clara, CA 95050
  • Job Code
Job Description

In this role you will be part of IP design validation team chartered with delivering IP to multiple server SOCs across Intel.

Responsibilities include although not limited to:

  • Define and enhance pre-silicon validation infrastructure and

  • methodologies of high complexity IP improving the overall efficiency

  • and velocity of the pre-silicon validation

  • Interact closely with the architecture and design teams understand

  • architectural and microarchitectural details to come up with

  • comprehensive test plans to validate the IP

  • Create define and develop IP validation environment and test suites

  • Development of methodologies execution of validation test plans test

  • sequences and directed tests

  • Mentor and guide junior verification engineers

The role requires the following attributes:

  • Proven track record in processor or IP verification from environment

  • development to tests development

  • Hands-on verification experience and high proficiency using System

  • Verilog and OVM UVM

  • Proven track record of developing complex verification collaterals

  • quickly and solid simulation debug skills

  • In-depth understanding of computer architecture PCIExpress

  • protocols and coherency protocols


You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

Bachelor's degree in Electrical Engineering or Computer Engineering or related discipline and 6+ years of relevant work experience; OR Master's degree in  Electrical Engineering or Computer Engineering or related discipline and 4+ years of relevant work experience; OR PhD in Electrical Engineering or Computer Engineering or related discipline and 2+ years of relevant work experience in the following:

  • Pre-Si Validation/Design

  • Software Programming

  • Hands-on verification using System Verilog and OVM /UVM

  • In-depth understanding of computer architecture

  • Experience leading a small/medium sized team.

  • Knowledge and understanding of PCI Express protocols and coherency protocols

Inside this Business Group

IP Engineering Group's (IPG) vision Build IPs that power Intel's leadership products and power our customer's silicon. We want to attract & retain talent who get joy in building high quality IP and share our core belief that IP is fundamental to transforming Intel's silicon design process. IPG's guiding principles will be ensuring Quality (Zero Bugs), Customer Obsession (Delight our Customers) and structured Problem Solving. We are a fearless organization transforming IP development.

Other Locations

US, Oregon, Hillsboro

Intel Corporation will require all new U.S. employees to be fully-vaccinated for Covid-19 as a condition of hire unless they have an approved accommodation in place under applicable law. Newly-hired employees will be required to provide proof of vaccination prior to their start date.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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IP Validation Lead Engineer

Santa Clara, CA 95050

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