IP Validation Design Engineer

Intel
Hillsboro, OR 97123
  • Job Code
    JR0180574
Job Description

In this position you will join the PESG Intel Technology Platform Management ITPM team responsible for developing and enabling SoC agnostic IP QA solutions on leading edge Intel technologies. You will work with IP SoC Platform methodology and design automation teams on requirements test scenarios, customer issues, and enhancement requests to IP QA system capabilities.

Responsibilities of the role include, although not limited to:

  • Deploying Platform IP QA solutions using internal and vendor tools to the IP design teams
  • Creating documentation and providing customer training as needed
  • Collaborating with various PESG tool owners to optimize IP QA signoff TFM and efficiency
  • Providing customer support and troubleshooting verification issues with various signoff flows

In addition to the qualifications listed below, the ideal candidate will also have:

  • Excellent verbal and written communication skills
  • Strong analytical problem solving and multitasking skills


Qualifications

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

The candidate must have a Bachelor's degree in Electrical, Electronics, Computer Engineering, Computer Science or a related field with 4+ years of experience -OR- a Master's degree in Electrical, Computer Engineering, Computer Science or a related field with 3+ years of experience in the following:

  • Relevant SoC and mixed-signal EDA tools and flows (Synopsys or Cadence or Mentor) including layout verification
  • Crossfire or equivalent tool
  • Programming and software development with Python, TCL or Perl

Preferred Qualifications:

  • Knowledge of SoC integration challenges, IP collateral requirements, and IP integration
  • Hands-on experience with industry standard ASIC and/or custom design and signoff on leading edge process technologies
  • Knowledge of industry standard EDA tools/flows for digital and/or analog design and signoff
  • Working experience of collaborating with process, design, and design automation teams

Inside this Business Group

The Design Engineering Group is a worldwide team responsible for the design, development, validation, and manufacturing of IPs and SOCs. Our mission is to deliver leadership products through groundbreaking innovations.



Other Locations

US, California, Santa Clara;US, Texas, Austin



Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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IP Validation Design Engineer

Intel
Hillsboro, OR 97123

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