IP Logic Design Engineer

Santa Clara, CA 95050
  • Job Code
Job Description

The Security Engineering team is looking for current and future digital logic design technical leaders and experts with experience in and/or exposure to pre/post-silicon validation + knowledge of scalable IP design. The role will be responsible for design of new IP roadmap features and develop secure design practices as part of Foundational Security Team's (FST) HW IP developing HW security for - several groups market segments across Intel.

As a member of the team, you will be responsible for:

  • Driving a scalable IP development while also making the Design Integration and SOC delivery a fully automated solution
  • Work closely with the Architect/Uarchitecture and Validation teams in determining the proper implementation strategy for new design, define and provide feedback on specifications
  • Develop White Box Coverage plans
  • Understand high level IP end-to-end flows and review design codes for efficiency/coverage and drive any paradigm shifts needed in correct-by-construction design implementation.
  • Engage with early prototyping (w/ FPGA, Emulation teams)
  • Be actively engaged in risk analysis and validation recommendation for product tapeouts etc.

In addition to the qualifications listed below, the ideal candidate will also have:

  • Excellent communication and organization skills are critical, along with teamwork, and must demonstrate strong technical leadership skills
  • Passion for design/ tools and methodology and strong influencing skills
  • Must have strong orientation for Quality and Commit and Deliver and Drive Innovation/efficiencies and have strong strategic thinking to come up with paradigm shift solutions to critical design/validation challenges


You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

Candidate must have a Bachelors' Degree in Electrical Engineering or Computer Engineering +3 years of experience; OR Master's Degree in Electrical Engineering or Computer Engineering with 2+ years of experience.

2+ years of experience in:

  • Relevant logic design position and must have gone through multiple project cycles to gather in-depth experience

  • In digital logic design with various tools and methodologies including: System Verilog, Perl, VCS/Synopsys simulators

  • Lint, Synthesis, Clock Domain Crossing tools, DFX Scan and Power.

  • Sub-system/ IP design and or verification

  • PC Architecture

Preferred Qualifications:

  • Knowledge of critical PC IO subsystems (e.g PCIe) and security algorithms (Crypto Engines) are highly recommended

  • Knowledge of IO Controllers and Design and experience with standard buses / bridges such as AHB / OCP / AXI are preferred

  • Knowledge of Low power / High Performance Designs and Practices are preferred

Inside this Business Group

In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intels products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moores Law and groundbreaking innovations.  DEG is Intels engineering group, supplying silicon to business units as well as other engineering teams.  As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.

Other Locations

US, California, Folsom

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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IP Logic Design Engineer

Santa Clara, CA 95050

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