IP Design Validation Engineer

Hillsboro, OR 97123
  • Job Code
Job Description

The world is transforming - and so is Intel! Intel is a company of bold and curious inventors and problem solvers who create some of the most astounding technology advancements and experiences in the world.With a legacy of relentless innovation and a commitment to bring smart, connected devices to every person on Earth, our diverse and brilliant teams are continually searching for tomorrow's technology and revel in the challenge that changing the world for the better brings. We work every single day to design and manufacture silicon products that empower peoples digital lives. Do you love to solve technical challenges that no one has solved yet? Do you enjoy working with cross functional teams to deliver IP solutions for products that impact customers lives? If so, Come join us to do something wonderful!

The CXL Cache Mem IP team (IPG) is looking for a passionate Verification Engineer. The candidate will be part of a silicon design team chartered with developing and delivering multiple generations of state of the art, highly configurable upstream and downstream Compute Express Link (CXL) cache and Mem IPs to multiple Intel server and client SOCs. This is a hands on, highly technical individual contributor role.

Responsibilities will include but not limited to:

  • Feature evaluations for complexity, effort and write test plans.
  • Own execution of features and drive validation test plans, test sequences and directed tests
  • .Interact and work closely with architect and design teams, influencing arch/uarch decisions to simply validation
  • Create, define and develop scalable and modular validation environment
  • Define, analyze and enhance methodologies for pre-silicon validation of IP. Bring creative initiatives to improve efficiency and velocity of the team.
  • Run focused technical working group meetings
  • Participate in improvements to the validation environment and retrospectives to drive down validation and design bug escape rates

The role requires the following attributes / qualifications:

  • Should have excellent problem solving skills, written and verbal communication.
  • Proven track record with developing modern constraint random verification environments with checkers/monitors/stimulus and driving execution with functional /code coverage and assertions.
  • Hands-on verification experience and proficiency using System Verilog or Specman using UVM is required.
  • Experience in development and deployment of verification strategies and methodologies across teams and organizations.
  • Ability to work in a dynamic environment, ability to understand abstract concepts and multitask.


This position requires meeting the below minimum qualifications to be initially considered. Preferred qualifications are in addition to the minimum requirements and are considered a major plus.

Minimum Qualifications:

Candidate must have a Bachelor's degree in Electrical / Computer Engineering with 4+ years' of experience -OR- a Master's degree in Electrical / Computer Engineering with 3+ years' of experience in:

  • Pre-silicon verification
  • Reading and interpreting technical specs and Register Transfer Level (RTL) code.
  • Debug, writing monitors/checkers/reference models / stimulus
  • Verifying standard IO protocols like PCIE / CXL / USB / Ethernet etc.
  • Developing test benches using System Verilog and UVM/OVM methodology, developing testplans and executing tests
  • Feature evaluations for complexity and effort
  • Programming and scripting with C/C++/Perl/Python

Preferred Qualifications: Experience in:

  • Global validation areas like power management, design for debug (DFD), DFT
  • Computer architecture and coherency protocols
  • Digital PHY validation
  • Performance validation
  • Supporting post-silicon bring up and debug.
  • Formal verification and assertion based verification

Inside this Business Group

IP Engineering Group's (IPG) vision Build IPs that power Intel's leadership products and power our customer's silicon. We want to attract & retain talent who get joy in building high quality IP and share our core belief that IP is fundamental to transforming Intel's silicon design process. IPG's guiding principles will be ensuring Quality (Zero Bugs), Customer Obsession (Delight our Customers) and structured Problem Solving. We are a fearless organization transforming IP development.

Other Locations

US, California, Santa Clara

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Before you go...

Our free job seeker tools include alerts for new jobs, saving your favorites, optimized job matching, and more! Just enter your email below.

Share this job:

IP Design Validation Engineer

Hillsboro, OR 97123

Join us to start saving your Favorite Jobs!

Sign In Create Account