IO Validation Engineer

Santa Clara, CA 95050
  • Job Code
Job Description

Join Intel and build a better tomorrow. Intel is in the midst of an exciting transformation, with a vision to create and extend computing technology to connect and enrich the lives of every person on Earth. So join us and help us create the next generation of technologies that will shape the future for decades to come.

Our Xeon Server Validation Team is seeking DDR memory, serial high, low speed and on package IO Validation Engineers to join us in our quest to ensure no bugs escape to our customers by validating the functional correctness of the digital logic of our CPUs.

We are comprised of engineers from a variety of life experiences and perspectives who share this common goal and pursue excellence in doing so.

We value our people first and foremost, so we appreciate a We-Over-Me mentality and a spirit of collaboration and encouragement. We have a robust server roadmap to deliver and therefore need your passion for problem-solving and your expertise.

If you are technically curious and enjoy developing creative solutions to complex problems, then come join us in delivering the highest quality server products to the world. In exchange, we offer you the opportunity to collaborate closely with the brightest minds in the industry, and to be a part of the work influencing the technology data revolution.

You will enjoy all the growth opportunities available to you at company as expansive and diversified as Intel.

Specific responsibilities include:

  • Develop and document electrical validation requirements, strategy and test plans for IO PHYs, for memory or serial I/Os, example DDR, PCIe, SPI.
  • Pre-Si development of analog test content at IP and full chip level, including test writing and validating through simulations.
  • Post-Si electrical validation of IO interfaces. Silicon debug to identify electrical, functional and DFT related bugs and silicon characterization to validate IO.
  • Investigate and resolve complex issues with hardware/BIOS/Firmware/Operating System implementations and recommends solutions. Use analysis to resolve electronic issues.
  • Support system and tester level validation teams to identify and close analog issues.
  • Collaborate with worldwide cross-functional teams including design, validation, software, manufacturing and product engineering, as you drive for test capability throughout the entire product development cycle.
  • Drive test optimizations to enhance product quality, improve efficiency and accelerate stability.
  • Analysis and disposition of early customer returns to drive understanding of design marginalities or develop test content to screen these units where needed.


Minimum Qualifications:
- BS in Electrical Engineering, Computer Engineering or Computer Science with 6+ years of experience, or MS in Electrical Engineering or Computer Engineering with 4+ years of experience.
- A developed understanding of Computer Architecture and CPU micro-architecture, logic/circuit design
- Experience in SOC design, verification or validation disciplines
- Hardware/Programming languages: Python, Verilog, C, C++, etc
- High and low speed circuit testing and system/platform level debug methodology and tools (analog probing, oscilloscope and JBERT usage, etc)
- Analog/logic design, validation or characterization
- DFT, hardware testing methods and tools
- Problem-solving, HW/SW/FW debug and logic proficiency
- Experience with hardware, system and/or microprocessor validation

Preferred knowledge in:
- PHY JEDEC standard protocol
- Data analytics
- BIOS or Firmware validation
- Test HW automation frameworks
- Linux OS, Windows OS
- Signal integrity and power delivery network

The ideal candidate needs to exhibit the following behavioral traits:
- A collaborative and helpful spirit
- Creativity
- Growth mindset
- Ability to use methodical approach to solve highly complex problems
- Excellent verbal, written, and interpersonal skills

Inside this Business Group

The Design Engineering Group is a worldwide team responsible for the design, development, validation, and manufacturing of IPs and SOCs. Our mission is to deliver leadership products through groundbreaking innovations.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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IO Validation Engineer

Santa Clara, CA 95050

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