Intel Standards Chief Architect

Intel
Santa Clara, CA 95050
  • Job Code
    JR0180948
Job Description

The datacenter architecture team at Intel is seeking a lead architect to own and drive the Intel interface and protocol standards for all Intel IPs, SoCs and help develop an industry ecosystem for these standards.

The ideal candidate for this role would bring several years of successful standards, IP and SoC development and enablement experience in the industry. Deep knowledge and direct contributions to industry standards such as AMBA, AXI, ACE, CHI, OCP, CXL, CCIX, PCIe, QPI/UPI, etc. will be a big plus. The architect will work closely with lead product and SoC architects at Intel and will be responsible for spearheading the definition of all SoC and IP interface and protocol standards and transformation of Intel's architecture to align with them. In addition, the architect will technically lead the industry ecosystem development around these standards with the enablement team. This role would reshape the Intel products to new levels of efficiency and standardization, and rapid market deployment with customers and partners. This standards development and industry enablement is at the center of the IDM 2.0 vision laid out by Intel CEO. It is a highly horizontal role covering many SoCs and IPs including client, server, graphics, core, fabric, memory, and IO, and processes around SoC integration, verification and automation. This is an excellent opportunity for star silicon architects with the hunger and desire to define and lead Intel's transformation in the era of IDM 2.0. This is also an excellent opportunity to join a highly inclusive team with one focus at Intel: the relentless pursuit of architecture innovations to satisfy the needs of next breed of cloud, hyperscale, web 2.0 and enterprise applications. The solutions developed by this team over the last decade have formed the foundation of modern datacenter architecture and led to rapid growth of both Intel's datacenter business and the overall cloud and datacenter industry. This dynamic role will involve direct working relationship with Intel senior management and Fellows with high visibility, impact and growth opportunities.


Qualifications

Minimum Qualifications
- Bachelor's degree in Computer Engineering, Electrical Engineering or related discipline and 9+ years' experience in SoC architecture, design and validation experience in semiconductor industry; OR Master's degree in Computer Engineering, Electrical Engineering or related discipline and 6+ years' experience in SoC architecture, design and validation experience in semiconductor industry; OR PhD degree in Computer Engineering, Electrical Engineering or related discipline and 5+ years' experience in SoC architecture, design and validation experience in semiconductor industry
- 8+ years' experience in multiple domains of the SoC architecture, datacenter product concepts, and compute protocols and interfaces standards
- 5+ years' experience in industry standards, tools and SoC design methodologies and manufacturing processes

Preferred Qualifications
- Knowledge and contributions to the industry standard memory, cache and CPU protocols such as CXL, AMBA, AXI, ACE, CHI, OCP, CCIX, PCIe, QPI/UPI, etc.
- Experience developing or contributing to the development of an industry ecosystem of IPs, VIPs and Drivers based on SoC protocol standards
- Experience developing SoCs and IPs based on industry standard interface and protocol standards

Inside this Business Group

The Design Engineering Group is a worldwide team responsible for the design, development, validation, and manufacturing of IPs and SOCs. Our mission is to deliver leadership products through groundbreaking innovations.



Other Locations

US, Oregon, Hillsboro;US, Texas, Austin



Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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Intel Standards Chief Architect

Intel
Santa Clara, CA 95050

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