IFS Mask Designer

Intel
Folsom, CA 95630
  • Job Code
    JR0193378
Job Description

As an integral part of Intel's new IDM2.0 strategy, we are establishing Intel Foundry Services (IFS), a fully vertical, standalone foundry business, reporting directly to the CEO. IFS will be a world-class foundry business and major provider of US and European-based capacity to serve customers globally. Intel Foundry Services will be differentiated from other Foundry offerings with a combination of leading-edge packaging and process technology, committed capacity in the US and Europe - available for customers globally - and a world-class IP portfolio that customers can choose from including x86 cores, graphics, media, display, AI, interconnect, fabric and other critical foundational IP, along with Arm and RISC-V ecosystem IPs. IFS will also provide access to silicon design services to help our customers seamlessly turn silicon into solutions, using industry-standard design packages.

This business unit is completely dedicated to the success of its customers with full P and L responsibilities. This model will ensure that our foundry customers' products will receive our utmost focus in terms of service, technology enablement and capacity commitments. IFS is already engaged with customers today starting with our existing foundry offerings and we are expanding imminently to include our most advanced technologies, which are optimized for cutting-edge performance, making them ideal for high-performance applications.

The IFS Foundry Engineering Technology & Customer Engineering team is looking for experienced Mask Designers whose responsibilities will include the development and preparation of multi-dimensional layouts and detailed drawings of semiconductor devices and microelectronic package assemblies.
Responsibilities may be directed at a specific point in the design cycle or vary as the project progresses through the design stages. Assignments are complex in nature. Work is performed within generally defined parameters. Acumen is required in resolving moderately complex problems. Normally receives general instructions on routine work and detailed instructions on new work.

Roles and Responsibilities:

  • Performs as a highly proficient technical individual contributor or specialist on complex layout and/or leadership assignments

  • Leadership responsibilities could include large-scale block layout, complex block layout, small to medium scope sections, small to medium scope projects, methodology development, tool evaluations, etc.

  • Given project conditions and constraints, develops detailed task lists, resource forecasts, and both short- and long-range schedules for sections and projects

  • Coordinate, facilitate, and monitor the daily activities of a small to medium group of support resources within their block, section, or project team

  • Expected to contribute to layout execution and a prominent level while holding a leadership position

  • Prioritizes workload of parallel tasks and responsibilities with minimal supervision

  • Manages daily operations within their assignments, showing appropriate consideration for established project objectives and standard project methodologies with minimal supervision

  • Able to develop the skills of less experienced layout designers through training, coaching, and mentoring

  • Proactively addresses and communicates issues impacting productivity and works to resolve roadblocks


Qualifications

Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

  • Minimum of 5 years of direct layout experience in advanced Semiconductor Process Node Technologies

  • Highly proficient with industry-based layout tools including Cadence Virtuoso, Synopsys, or similar

  • Highly proficient with industry-based verification tools including Calibre DRC, LVS, ANT/NAC, DEN, or similar


Preferred Qualifications:

  • Intel or TSMC Process experience highly desired

  • 2-year technical degree in VLSI or Physical Design/Mask Design

  • Experience in block, section, and/or chip level ownership, including forecasting, scheduling, and execution

  • Experience with tight pitch, highly sensitive layouts, i.e. decoder, sram layout

  • Experience with routing/floor-planning tools, i.e., Pulsic, ICC2, Fusion Compiler, etc.

  • Strong engineering problem solving and analytical skills

  • Knowledge of CMOS and VLSI component design principles

  • Experience with basic electronic circuit functionality and behaviors (passive and active circuit structures)

  • Strong background in analog design and layout guidelines (matching, symmetry, shielding, and timing)

  • Ability to work with abstract concepts or instructions

Inside this Business Group


Intel Corporation will require all new U.S. employees to be fully-vaccinated for Covid-19 as a condition of hire unless they have an approved accommodation in place under applicable law. Newly-hired employees will be required to provide proof of vaccination prior to their start date.



Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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IFS Mask Designer

Intel
Folsom, CA 95630

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