Graphics Hardware Timing Signoff Methodology Engineer

Folsom, CA 95630
  • Job Code
Job Description

If you are passionate about computer graphics and working with leading graphics engineers on Intel's latest GPU/CPU architecture, then our Graphics & Throughput Computing Hardware Engineering (GTCHE)  team has opportunities for you. We are passionate about delivering best-in-class visual experiences for users to immerse themselves. The Visual and Machine Learning IP team is within GTCHE delivering discrete and integrated graphics IPs to the client and datacenter markets.

In the role of a Graphics Hardware Timing Signoff Methodology Engineer you will be part of a world-class IP physical design team developing groundbreaking high-performance GPU/GFX IPs targeted at High-End Graphics, Gaming, Artificial Intelligence, Media processing, and more. This is a great opportunity to join a talented team that is innovating in ASIC implementation and verification of multi-million gate designs in advanced process nodes across multiple foundries.

Your responsibilities may include, but not be limited to:

  • Defining and implementing signoff methodology for signoff areas of Static Timing Analysis, ERC Quality and Parasitic Extraction across internal and external foundry processes

  • Developing STA flows and enabling validation of the flows through automation & regression setup

  • Collaborating with 3rd party EDA vendors to resolve issues and drive feature improvements in signoff tools

  • Debug/Analysis of signoff quality and supporting design execution teams

  • Documentation of design methodologies & flows

Behavioral traits that we are looking for:

  • Self-motivated individual who can demonstrate strong willingness to learn and contribute quickly

  • Excellent interpersonal communication skills Strong analytical and problem-solving skills to solve complex issues in a timely manner


Minimum skills and experience required to get you noticed:

This position requires a Bachelors degree in Electrical/ Electronics, Computer Engineering, or related discipline with 3+ years of educational or work experience or a Masters degree in the same fields, with 6+ months of educational or work experience. 

Your experience should be in one or more of the following areas: 

  • ASIC flow cycle with strong understanding of timing analysis concepts

  • EDA tool knowledge: Primetime, Tempus, STAR-RC, DC, ICC2, FusionCompiler, Innovus, or Genus  

  • Automation/scripting skills: TCL, Perl, Shell or Python for robust flow implementation, preferably TCL

Preferred Skills & Experience:

  • STA flow development or timing convergence

Inside this Business Group

Intel Architecture, Graphics, and Software (IAGS) brings Intel's technical strategy to life. We have embraced the new reality of competing at a product and solution levelnot just a transistor one. We take pride in reshaping the status quo and thinking exponentially to achieve what's never been done before. We've also built a culture of continuous learning and persistent leadership that provides opportunities to practice until perfection and filter ambitious ideas into execution.

Other Locations

US, Arizona, Phoenix;US, California, Santa Clara

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Before you go...

Our free job seeker tools include alerts for new jobs, saving your favorites, optimized job matching, and more! Just enter your email below.

Share this job:

Graphics Hardware Timing Signoff Methodology Engineer

Folsom, CA 95630

Join us to start saving your Favorite Jobs!

Sign In Create Account