Full Chip Codesign Power Integrity Engineer

Intel
San Jose, CA 95113
  • Job Code
    JR0183280
Job Description

As a member of the full chip team, you will be responsible for bump and ball planning, die package co-design analysis and implementation, full chip power intent methodology, IR drop analysis and verification.


Responsibilities include die-package-board pintable definition, implementation and verification, power electrical rules checking and IR drop analysis for power grid integrity.


Qualifications

You must possess minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your school work/classes/research and/or relevant previous job and/or internship experiences.

This is an entry level position and will be compensated accordingly.


Minimum Requirements:

  • Master's or PhD degree in Electrical Engineering, Computer Engineering or related field.


Minimum of 6+ months experience in:

  • TCL or Python.

  • Circuit design.

  • Spice.


Preferred Qualifications:

  • Unified Power Format (UPF).

Inside this Business Group

The Programmable Solutions Group (PSG) was formed from the acquisition of Altera. As part of Intel, PSG will create market-leading programmable logic devices that deliver a wider range of capabilities than customers experience today. Combining Altera's industry-leading FPGA technology and customer support with Intel's world-class semiconductor manufacturing capabilities will enable customers to create the next generation of electronic systems with unmatched performance and power efficiency. PSG takes pride in creating an energetic and dynamic work environment that is driven by ingenuity and innovation. We believe the growth and success of our group is directly linked to the growth and satisfaction of our employees. That is why PSG is committed to a work environment that is flexible and collaborative, and allows our employees to reach their full potential.



Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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Full Chip Codesign Power Integrity Engineer

Intel
San Jose, CA 95113

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