Frontend Infrastructure Lead

Intel
San Jose, CA 95113
  • Job Code
    JR0168603
Job Description

The Front-end Infrastructure Lead will support FPGA development projects with industry leading frontend design entry, checking, and release methods. You will be the organizations expert to spread industry best practices for RTL design to the products of the Programmable Solutions Group supporting FPGAs. You will demonstrate the expertise to recommend RTL coding practices that provide better efficiency for downstream flows (for example, design-for-test, design verification, emulation, and place-and-route physical implementation Experience using Synopsys VCS, Cadence NC-Sim, or Mentor Questa simulators.) You must understand inefficiencies that design teams currently face, orchestrate solutions, and align the organization to these solutions. You will work cross functionally with the Software organization and other groups to support a development ecosystem for Intel's FPGA customers.


Qualifications

Qualifications

You must possess the minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Education Requirement:

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field

Minimum Requirements:

9+ years of RTL design experience if you have a bachelors degree, or 8+ years of RTL design experience if you have a Masters degree

2+ years of supporting RTL Development Teams

5+ years of experience organizing RTL source into reliable project build recipes for various end targets (example end targets: verification, emulation, and synthesis)

Preferred Qualifications:

Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field

Experience with RTL design release process and able to promote industry best practices
Experience with scripting languages to customize EDA tool usage and to develop wrapper flows

Inside this Business Group

The Programmable Solutions Group (PSG) was formed from the acquisition of Altera. As part of Intel, PSG will create market-leading programmable logic devices that deliver a wider range of capabilities than customers experience today. Combining Altera's industry-leading FPGA technology and customer support with Intel's world-class semiconductor manufacturing capabilities will enable customers to create the next generation of electronic systems with unmatched performance and power efficiency. PSG takes pride in creating an energetic and dynamic work environment that is driven by ingenuity and innovation. We believe the growth and success of our group is directly linked to the growth and satisfaction of our employees. That is why PSG is committed to a work environment that is flexible and collaborative, and allows our employees to reach their full potential.



Other Locations

US, Oregon, Hillsboro;US, Texas, Austin



Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Before you go...

Our free job seeker tools include alerts for new jobs, saving your favorites, optimized job matching, and more! Just enter your email below.

Share this job:

Frontend Infrastructure Lead

Intel
San Jose, CA 95113

Join us to start saving your Favorite Jobs!

Sign In Create Account