Front End RTL Design Automation Engineer

Intel
Hillsboro, OR 97123
  • Job Code
    JR0178769
Job Description

The Advanced Architecture Development Group (AADG) is a CPU Core development team in Portland, Oregon. If you are excited about advanced development of breakthrough technologies for future-generation CPU cores, please join us. We believe that developing these technologies takes a team of exceptionally talented individuals who work together to visualize, innovate, and make the future of computing possible. Join us to do something wonderful.

As part of our team, you will drive tool, flow, and methodology (TFM) enabling efforts for RTL and Design Validation (DV) needs. Responsibilities will include enabling and supporting the design environment, infrastructure, data managements solutions, EDA tools, and flows along with creating new methods for design automation towards best in class model simulation, validation, and continuous integration flows. Machine Learning techniques and Compute efficiency methods will be used to improve overall turn around time and ease of use for the RTL and Validation engineers. You will also be responsible for testing, deploying, and supporting production worthy flows to the team. This requires expertise in industry standard EDA and internal CAD technologies including code generator tools for registers, interfaces, and DFx; simulation tools such as VCS and Xcelium; static tools for lint, low power (LP), cross domain clocking checks (CDC), and DFx flows. This additionally requires a high level understanding of verification methodologies and tools such as UVM, design exercise and unit testing solutions, formal verification tools, emulation, fpga, and regression collection, bucketing, and coverage metric solutions. Bonus points if you understand synthesis and PlaceRoute flows, Timing, Central Runs, LV and RV enabling, and all other structural/RTL2GDS construction and verification tape-in activities. Expertise with scripting (Perl or Python) is a must.


Qualifications

Bachelor of Science degree in Electrical Engineering or Computer Engineering with 8 years of experience in IC Design, ASIC or Computer Aided Design (CAD) Or a Master of Science with 6 years of experience

  • Experience with latest industry tools from either Cadence, Synopsys or Mentor.

  • Expertise in industry standard EDA and internal CAD technologies including code generator tools for registers, interfaces, and DFx; simulation tools such as VCS and Xcelium; static tools for lint, low power (LP), cross domain clocking checks (CDC), and DFx flows.

  • High level understanding of verification methodologies and tools such as UVM, design exercise and unit testing solutions, formal verification tools, emulation, FPGA, and regression collection, bucketing, and coverage metric solutions

  • Excellent programming skills: Unix, Perl, Python, Tcl or other

  • Practical experience with data management software is expected Git, Perforce, etc.


Preferred skills:

  • Understanding of Structural/RTL2GDS tools and flows for construction and verification towards silicon tape-in, for example synthesis, APR, floor planning, timing, central runs, LV and RV flows, and all other tape-in activities.

  • Demonstrate experience to interface with engineers, senior managers and stakeholders

  • Demonstrate experience to mentor, coach and lead small groups of junior engineers working across Intel sites

Inside this Business Group

Intel Architecture, Graphics, and Software (IAGS) brings Intel's technical strategy to life. We have embraced the new reality of competing at a product and solution levelnot just a transistor one. We take pride in reshaping the status quo and thinking exponentially to achieve what's never been done before. We've also built a culture of continuous learning and persistent leadership that provides opportunities to practice until perfection and filter ambitious ideas into execution.



Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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Front End RTL Design Automation Engineer

Intel
Hillsboro, OR 97123

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