FPGA Design Engineer

San Jose, CA 95113
  • Job Code
Job Description

The Intel Programmable Solutions Group (PSG) has been delivering industry leading custom logic solutions to customers since inventing the world's first reprogrammable logic device in 1984. The mission of PSG is to drive the future for FPGA and Intel eASIC technology/solutions around the globe. Within PSG, you'll be surrounded by some of the brightest minds/engineers in the world.

The PSG Custom Logic IP Solutions team is seeking a motivated FPGA Design Engineer to join our team to work on the SmartNIC solutions based on the cutting-edge FPGAs.

As a FPGA Design Engineer, you will

  • Work with micro-architects, software engineers, verification engineers and physical design engineers to implement the vertical IP subsystems for our acceleration development platforms, within a culture of industry standard best practices and methodologies.

  • Design and write well-documented, high quality and FPGA-friendly RTL.

  • Define timing constraints and working with physical design engineers for design implementation

  • Work with the Design Verification team to review test plans and assist in test failure debug.

  • Support the platform validation team to define validation strategies, test plans, quality reviews and assist with debug when necessary.


Relevant experience can be obtained through schoolwork, classes, project work, internships, and/or military experience. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.


Bachelors Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field

Minimum Qualifications

  • 3+ years of experience in logic design and debug using Verilog and/or System Verilog (or Masters Degree with an internship or 1+ year of experience)

  • Experience with FPGA/ASIC and the associated design tools (e.g. Quartus, Vivado, Design Compiler, etc.)

Preferred Qualifications

  • 5+ years of experience in logic design and debug using Verilog and/or System Verilog

  • Experience with micro-architecture definition

  • Experience with high speed serial communication protocols

  • Experience with timing closure and hardware debug

  • Experience with micro-architecture definition

  • Experience with high speed serial communication protocols (e.g. PCIe, Ethernet, Memory, SerDes, etc.)

Inside this Business Group

The Programmable Solutions Group (PSG) was formed from the acquisition of Altera. As part of Intel, PSG will create market-leading programmable logic devices that deliver a wider range of capabilities than customers experience today. Combining Altera's industry-leading FPGA technology and customer support with Intel's world-class semiconductor manufacturing capabilities will enable customers to create the next generation of electronic systems with unmatched performance and power efficiency. PSG takes pride in creating an energetic and dynamic work environment that is driven by ingenuity and innovation. We believe the growth and success of our group is directly linked to the growth and satisfaction of our employees. That is why PSG is committed to a work environment that is flexible and collaborative, and allows our employees to reach their full potential.

Other Locations

US, California, Santa Clara

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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FPGA Design Engineer

San Jose, CA 95113

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