Forward Error Correction (FEC) SoC Design Engineer

San Jose, CA 95113
  • Job Code
Job Description

Oversees definition, design, verification, and documentation of state-of-the-art Forward Error Correction (FEC) and Ethernet physical layer IP for next generation FPGA families. Analyzes complex FEC algorithms and develops parameterizable and efficient IP implementations, for both ASIC and FPGA. Defines and develops future FEC cores. Determines microarchitecture design, logic design, RTL coding, and system simulation. Performs all aspects of the design flow from high level design to synthesis. Oversees physical design place and route, and timing and power model generation. Participates in planning and execution of design verification and silicon validation. If you have strong Reed-Solomon background, and a passion for cutting-edge FEC development, the Intel Programmable Solutions Group would love to speak with you.


Minimum Qualifications:

3+ years of experience with:


High-speed forward error correction (FEC) blocks, especially Reed-Solomon codecs; the ideal candidate will also have a strong theoretical background in this area


1+ years of experience with the following:


Hardware design experience in RTL, preferably on large complex designs

Digital design flows including RTL simulation, timing constraints

BS required, M.Sc.; Ph.D. in relevant subject area strongly preferred



Preferred qualifications:


Familiarity with ASIC design flows (libraries, EDA tools, verification methods, etc.)
Broad FEC background (Viterbi, LPDC, etc.)

Working understanding of IEEE Ethernet standards



Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and/or schoolwork/classes/research.

Inside this Business Group

The Programmable Solutions Group (PSG) was formed from the acquisition of Altera. As part of Intel, PSG will create market-leading programmable logic devices that deliver a wider range of capabilities than customers experience today. Combining Altera's industry-leading FPGA technology and customer support with Intel's world-class semiconductor manufacturing capabilities will enable customers to create the next generation of electronic systems with unmatched performance and power efficiency. PSG takes pride in creating an energetic and dynamic work environment that is driven by ingenuity and innovation. We believe the growth and success of our group is directly linked to the growth and satisfaction of our employees. That is why PSG is committed to a work environment that is flexible and collaborative, and allows our employees to reach their full potential.

Intel Corporation will require all new U.S. employees to be fully-vaccinated for Covid-19 as a condition of hire unless they have an approved accommodation in place under applicable law. Newly-hired employees will be required to provide proof of vaccination prior to their start date.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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Forward Error Correction (FEC) SoC Design Engineer

San Jose, CA 95113

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