ENGINEERS

Xilinx, Inc
San Jose, California
  • Job Type
    Employee
  • Job Status
    Full Time
  • Shift
    1st Shift

Xilinx, Inc. in San Jose seeks:

 

Staff Verification Engineer (job code 81865). Create verification plans at the block level. Reqs incl. BS or fgn equiv in CS, Electrical Engg, or rel + 5 yrs prog rel exp, or MS + 3 yrs rel exp.  

 

IC Design Engineer (job code 81924). Design, develop, or test electronic components & syss. Req MS or fgn equiv in Electrical Engg, CS, or rel field.

 

Staff (Design for Testing) Engineer (job code: 81311). Work on state of art SERDES, high speed ADC/DAC, & next generation DDR tech in 16nm & 7nm processes. Reqs incl BS or frgn equiv. in CS, Elctrcl Engg, or rel + 7 yrs prog rel exp. Will also accept MS or frgn equiv. in CS, Elctrcl Engg, or rel + 5 yrs prog rel exp.

 

Staff Process Device Engineer (job code: 80997). Wrk w/ internal teams & foundry in handling advncd CMOS techn node dvlpmnt (16 mm and beyond), characterization & definition. Reqs incl MS or frgn equiv. in Electronics Engg, Materials Sci, or rel + 5 yrs rel exp.

 

Staff Hardware Development Engineer (job code 81992). Resp for hardware design, dvlpmt & testing board prods using Xilinx FPGAs, MPSoC, RFSoC, & other devices. Reqs incl BS or frgn equiv in Eltrncs Eng, Eltrcl Eng or rel + 5 yrs prog rel exp.

 

Sr. Staff Design Engineer (job code: 82274). Manage back end deliverables for Digital Signal Processing IP blocks. Reqs incl MS or frgn equiv. in CS, Elctrcl Engg, or rel + 8 yrs rel exp. Will also accept BS or frgn equiv. in CS, Elctrcl Engg, or rel + 10 yrs prog rel exp.

 

Design Engineer (Design and Verification) (job code 79835). Oversee define, design, verify, and doc ASIC devlpmnt. MS or fgn equiv in CE, Electrical Engg, or rel.

 

Senior Design for Test Engineer (job code 80275). Resp for config, prog and diag of CRAM thru C code. Reqs incl MS or frgn equiv in Comp Sci/Eng, Eltrcl Eng or rel + 2 yrs rel exp.

 

Senior Design Engineer [multiple openings] (job codes 79828, 79869). Leverage RTL base design expertise & take high perf embed IPs from des thru synth., layout & full timing closure using adv proc nodes. MS or fgn equiv in Electrical Engg, CE, Computing, or rel +1 yr rel exp.

 

Mail resume to Xilinx, Inc. Attn: Staffing Services at 2100 Logic Drive, San Jose, CA 95124-3450. Must reference the relevant job code to be considered. EEO/AA/Vet/Disability Employer.

 

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ENGINEERS

Xilinx, Inc
San Jose, California

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