E-Core CPU DFT Validation engineer

Austin, TX 78701
  • Job Code
Job Description

Your responsibilities may include, but are not limited to, the following:

  • Technical ownership of validation of a microarchitecture block, methodology, or otherwise significant aspect of CPU design
  • Understand and contribute to micro-architecture specification and define verification strategy for a significant portion of the design
  • Lead ROI analysis and recommend appropriate use of formal verification vs dynamic validation techniques for relevant parts of the CPU
  • Document test plans and drive technical reviews of plans with design and architecture teams
  • Develop validation content like directed tests, test benches, test generators, and automation tools to accelerate execution
  • Analyze and use results to modify testing
  • Influence and contribute to post-silicon validation
  • Post-silicon failure debug and sighting resolution
  • Mentor junior team members
  • Collaborate on validation approach and strategy beyond immediate team


You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

The candidate must have a Master's in Electric Engineering, Computer Science, Computer Engineering.

3+ years of experience in :

  • Validation, preferably on the CPU
  • CPU micro-architecture knowledge in areas such as out-of-order execution, power management, DFT, system debug, ATPG, BIST, UPF, low power design, processor pipelines, Memory load and store, Cache Coherency, Paging etc.
  • PreSi System Verilog RTL verification flow and environments, including test plans, test writing, and Coverage
  • CPU assembly, Verilog and/or System Verilog, OVM, Perl, Linux, hardware modeling, and Assertions

Preferred Qualifications:

1+ years of experience in:

  • Closely-related areas such as SOC subsystem design or validation will also be considered
  • Experience in testbench architecture and hands-on development of components like BFMs, checkers, transactors, monitors and others using verification methodologies like System-Verilog, VMM/OVM/UVM or equivalent is highly desirable
  • Proficiency in independent debug of System Verilog RTL failures to root-cause functional bugs
  • Directed or Constrained-Random test-writing skills
  • Research publications, patent filings, or other evidence of personal technical innovation in validation methodology advancement

Inside this Business Group

The Devices Development Group (DDG) is a global organization focused on the development and integration of SOCs, critical IPs including Atom and chipsets that power Intel's leadership products. This business group leverages an incomparable mix of experts with different backgrounds, cultures, perspectives, and experiences to unleash the most innovative, amazing, and exciting computing experiences.

Intel Corporation will require all new U.S. employees to be fully-vaccinated for Covid-19 as a condition of hire unless they have an approved accommodation in place under applicable law. Newly-hired employees will be required to provide proof of vaccination prior to their start date.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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E-Core CPU DFT Validation engineer

Austin, TX 78701

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