Summary

Posted: Jan 7, 2021

Role Number:200214306

Join our team at Apple developing custom mixed-signal integrated circuits for Apple's existing and future product lines. Our small ...Summary

Summary

Posted: Jan 7, 2021

Role Number:200214306

Join our team at Apple developing custom mixed-signal integrated circuits for Apple's existing and future product lines. Our small team has already shipped hundreds of millions of chips into several Apple product lines, including new products launched this year.

As a member of our mixed-signal ASIC team, you will be responsible for designing complex digital IP's for Apple power conversion and management IC's. You will work with the system architects, product teams, verification engineers, and analog designers, creating block level specifications and implementing the designs. You will own the creation of the blocks, and take them through the concept, implementation, and validation phases, and then into mass production. Learn and use state of the art digital and mixed-signal tools and development flows to implement your designs.

Although the team is small, we supply silicon to most of Apple's industry leading hardware development teams. We have a close-knit, robust team in need of experience digital design engineers to lead the development of new IP's and mentor junior engineers entering the mixed signal ASIC development field. Join us in building Apple's next generation products. Do you want to be a part of building the "surprise and delight" in Apple's future products?

Key Qualifications

• Ten or more years developing digital IP's for SoC's or mixed signal IC's
• Experience mentoring or leading junior design or verification engineers
• Proven track record shipping quality designs on schedule
• Experience with synthesis and static timing tools
• Expertise in Clock Domain Crossing design and verification techniques
• Experience with power estimation tools and techniques
• Familiarity with silicon development milestones and project resource management
• Good understanding of low power design techniques including clock and power gating. Familiarity with UPF based power intent specification and power verification
• Some familiarity with mix-signal ASIC design and asynchronous analog / digital interfaces is helpful, but not required

Deliver complex digital control blocks, meeting schedule, area, power, and performance targets
Collaborate in developing precise design specifications for digital control blocks
Implement FSM's and other control logic in System Verilog
Collaborate with managers and program managers to track progress and gauge tapeout readiness
Work with DV teams to create verification plans
Work with silicon validation team in developing lab validation and qualification plans
Work with test team in developing implementation plans for ATE test programs

Education & Experience

MSEE required

Additional Requirements