DFT DFx Verification Engineer Lead

San Jose, CA 95113
  • Job Code
Job Description

As a Senior DFT/DFx Verification Engineer Lead you will be responsible for driving and execution of DFx verification flow and implementations at block level and full chip level. You will be expected to be hands-on, use tools, participate in high-level silicon specifications, work closely with SoC architects and digital block leads to provide the best input for DFx verification scope and effort, and possess the skills to independently carry entire DFx verification toward the success of silicon tape-out/tape-in with world-class commercial quality.

Your responsibilities as Senior DFT/DFx Verification Engineer Lead will include the followings:

  • Work closely with cross functional teams in understanding the DFT architecture and planning the verification tasks for the entire DV team.

  • Work with the digital design teams on understanding design in context of DFx implementations. Work with Post-si validation and design team to establish requirements for DFD (Design for Debug).

  • Work with DFx verification team to initiate DFx TFM (Tools, flows, methodologies)

  • Develop new scripts/flows to improve DFx verification

  • Establish DFx simulation environment including new techniques and methods, and validate the DFx designs

  • Generate and deliver the test simulation environment for downstream partners such as manufacturing teams.

  • Be a good team player with excellent interpersonal and communication skills to work with cross-functional partners and core-team/PDT


Relevant experience can be obtained through schoolwork, classes, project work, internships, and/or military experience. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.


Bachelors Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field

Minimum Qualifications:

10+ years of experience, experience should include

  • Pre/Post Si DFT/DFx experience (insertion, verification, coverage, debug, production test vector generation).

  • MBIST architecture, JTAG, and/or Boundary scan verification using CAD Tools

Preferred Qualifications:

Experience in one or more of the following is a plus

  • Experience with FPGA products

  • Experience with design integration process.

  • Experience with firmware and/or Physical Design (DFx impact)

  • Experience with multi-team, global multi-site working environment

  • Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field

Inside this Business Group

The Programmable Solutions Group (PSG) was formed from the acquisition of Altera. As part of Intel, PSG will create market-leading programmable logic devices that deliver a wider range of capabilities than customers experience today. Combining Altera's industry-leading FPGA technology and customer support with Intel's world-class semiconductor manufacturing capabilities will enable customers to create the next generation of electronic systems with unmatched performance and power efficiency. PSG takes pride in creating an energetic and dynamic work environment that is driven by ingenuity and innovation. We believe the growth and success of our group is directly linked to the growth and satisfaction of our employees. That is why PSG is committed to a work environment that is flexible and collaborative, and allows our employees to reach their full potential.

Other Locations

US, Oregon, Hillsboro;US, Texas, Austin

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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DFT DFx Verification Engineer Lead

San Jose, CA 95113

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