DFM/Collateral Engineer

Intel
Santa Clara, CA 95050
  • Job Code
    JR0182122
Job Description
Job Description

This position is associated with the sale of Intel's NAND memory and storage business to SK Hynix (You can read more about the transaction in the press release - https://newsroom.intel.com/wp-content/uploads/sites/11/2020/10/nand-memory-news-q-a.pdf). The transaction will enhance the resources and potential of the business' storage solutions, including client and enterprise SSDs, in the rapidly growing NAND Flash space amid the era of big data.

This is an exciting time to be at Intel! Come join our NAND DESIGN TECHNOLOGY and MANUFACTURING team as a Sr Product Engineer and work on the most advanced 3DNAND and SSD technology in the world.

As the global leader in the semiconductor industry Intel possesses industry leading Solid State Device (SSD) technology and the most capable NAND Flash products. As a Product Engineer, you will be part of a world class team that will transition to lead the SSD business at SK Hynix.

This position aligns to Phase 2 of the transaction, which includes NAND technology and component development along with fab operations. Employees aligned to Phase 2 will continue to be employed by Intel and will continue to develop NAND technology and components and manufacture NAND wafers at the fab. Phase 2 of the transaction is expected to close in March 2025, at which time employees aligned to this phase of the transaction will transition employment to SK Hynix.

Non-Volatile Memory Device and Integration engineers are responsible for leading research and development in order to architect, develop and deliver leading edge nonvolatile memory technologies to high volume manufacturing. They contribute to defining process and device architectures, technology collaterals as well as develop scaling paths for leading edge memory technologies.

The scope includes development of new types of process and device architectures involving novel materials, structures and integration schemes to deliver industry leadership in density, performance, reliability and cost. They collaborate with technology development partners in defining goals, developing the vision, aligning strategy and driving fast paced silicon development to meet aggressive technology node cadences. In addition they work closely with the product and system teams to ensure seamless integration of the memory components into Intel's system products as well as with the manufacturing Fabs to ensure a seamless technology transfer and ramp to support the full envelope of component and system products.

This particular role responsibilities include:

  • Develop and maintain scribe test structure, path finding test chips, alignment structures, registration boxes across various part types.
  • Use DF2, Cadence, K2View, Vcats, to develop the scribe layout.
  • Perform DRC checks, layout vs. schematic and netlist extraction tools to ensure correctness in layout of scribe test structures.
  • Apply working knowledge of skill code and Perl or C++ along with basic UNIX fundamentals in debugging database issues and DRCs/generators and provide feedback.
  • Create pcell spreadsheets and CDF interfaces to create test structures and also be involved with documentation of test structures built using auto-extraction tools.
  • Interface with multiple other groups like Process Integration, Design Rules, CAD, Layout, Scribe and Mask shops with patience and thoroughness.
  • Drive diagnostic projects across multi-disciplinary teams to understand product and test structure failures and their interaction with layout and mask synthesized data.


Qualifications

Minimum Qualifications:

  • BS + 5 Years integration, device, layout, circuit design skills


Preferred Qualifications:

  • In-depth knowledge of NVM device architecture including test structures, alignment structures, registration boxes.
  • In-depth knowledge of DRC/LVS, can fix most DRC/LVS issues that come up; work with the LVS/DRC maintenance group to build new models as needed.
  • Some understanding of generators and how they are related to process is helpful to fix any DRC/LVS issues.
  • In-depth knowledge of CAD tools and software, in particular DF2, K2view and Hercules.
  • Basic knowledge of device physics and parametric analysis.
  • Basic knowledge of photolithography and reticle creation.
  • Good verbal and written communication skills with Excel, Visio Power Point proficiency.
  • Familiarity of Tape-out, OPC and Mask Generation Flows for High volume manufacturing.
  • Good understanding of GDS2/SF/OASIS format and layout hierarchy and layer maps.
  • Knowledge of DFII, K2VIEW and other Industry standard CD capture/measurement tools.
  • Good verbal and written communication skills with Excel, Visio, Power Point proficiency.
  • Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.

Inside this Business Group

Non-Volatile Solutions Memory Group:  The Non-Volatile Memory Solutions Group is a worldwide organization that delivers NAND flash memory products for use in Solid State Drives (SSDs), portable memory storage devices, digital camera memory cards, and other devices.  The group is responsible for NVM technology design and development, complete Solid State Drive (SSD) system hardware and firmware development, as well as wafer and SSD manufacturing.



Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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DFM/Collateral Engineer

Intel
Santa Clara, CA 95050

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