Design Verification Engineer

Santa Clara, CA 95050
  • Job Code
Job Description

Come join a creative team of engineers dedicated to designing the hardware technologies that network the leading cloud-service datacenters. We are looking for a motivated and astute individual to join our team as a Verification Engineer. You will be joining a collaborative team responsible for building the world's leading programmable Ethernet switches. Our organization works on all levels of ASIC development, starting from high-level architecture to low-level circuit design and high-volume manufacturing.

Our verification engineers are responsible for building efficient and effective directed and constrained-random validation environments that exercise designs through their corner-cases and demonstrate conformance to specifications. They use their analytic and waveform analysis skills, strong knowledge of digital design, understanding of object-oriented programming, and detailed understanding of IEEE and IETF specifications to verify large networking ASICs comprised of tens of billions of transistors. You will be responsible for development of UVM unit-level benches and tests, developing test plans, coverage plans and coding functional coverage.

The ideal candidate should exhibit the following behavioral traits:

  • Detail oriented problem solving and communication skills.
  • Work independently and at various levels of abstraction.
  • Thoughtful and perceptive analytical responses.
  • A genuine curiosity for understanding the system.
  • Dedicated and committed to creative problem solving and assuming responsibility.


Candidates must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Requirements listed below would be obtained through a combination of Industry job-relevant experience, internship experiences, and / or school work classes /research.

Education Qualifications:

  • Bachelor's degree in Electrical or Computer Engineering, Computer Science, Math, Physics, or related field and 6+ years of industry work experience, or 
  • Master's degree in Electrical or Computer Engineering, Computer Science, Math, Physics, or related field and 4+ years of industry work experience, or
  • PhD in Electrical or Computer Engineering, Computer Science, Math, Physics, or related field and 2+ years of related work experience.

Minimum Required Qualifications

  • 5+ years of experience in System Verilog and UVM.
  • 5+ years of experience in developing functional coverage plans and coding coverage.

Preferred Qualifications:

  • 10+ years of experience in VMM / OVM / UVM.
  • 3+ years of experience in Switch Silicon verification.
  • 3+ years of experience in C or C++ for verification.
  • Experience with scripting languages, e.g. Python.
  • Experience with Synopsys simulation and coverage tools.

Inside this Business Group

The Data Center Group (DCG) is at the heart of Intels transformation from a PC company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologiesspanning software, processors, storage, I/O, and networking solutionsthat fuel cloud, communications, enterprise, and government data centers around the world.

Other Locations

US, Arizona, Phoenix;US, California, Folsom;US, California, San Jose;US, Oregon, Hillsboro

Intel Corporation will require all new U.S. employees to be fully-vaccinated for Covid-19 as a condition of hire unless they have an approved accommodation in place under applicable law. Newly-hired employees will be required to provide proof of vaccination prior to their start date.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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Design Verification Engineer

Santa Clara, CA 95050

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