Design Verification Engineer

San Jose, CA 95113
  • Job Code
Job Description

As a Design Verification Engineer  you will be working alongside a World-class FPGA team within the Programmable Solution Group (PSG) Custom IP & Solution Engineering (CISE) organization delivering on next-generation IPs, Subsystems, & Solutions to various PSG Business Units (BUs).

The Design Verification Engineer role calls for expertise in verification methodologies, architecture, and UVM constructs to build scalable & reusable verification collaterals. Close collaboration with the micro-architect and design teams to develop robust verification strategy, defining test plans, test writing, and debug in accordance to CISE's IP PLC. Develop comprehensive solutions to problems utilizing formal education and judgement. Capacity to work with and respond to requests from various internal teams across multiple sites is required.

Your responsibilities will include, but are not limited to:

  • Ensuring the logical design of an IP/subsystem/SoC satisfies the architectural specification

  • Creating and optimizing the verification environment, tools, and methodologies

  • Developing or using checking software to compare model behavior against a specification

  • Generating focused and random test cases, analyzing coverage, and debugging failure cases

  • Writing software to provide controllability and observability into the architectural model

  • Analyzing microarchitectural features to identify possible problem areas

  • Effective communication and teamwork skills.


You must possess the below minimum education requirements and minimum required qualifications to be initially considered for this position. Relevant experience can be obtained through schoolwork, classes, project work, internships, and/or military experience. Additional preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.


Bachelors Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field

Minimum Qualifications

5+ years of experience on ASIC or FPGA, IP design, and/or verification with experience in:

  • Logic Design verification

  • Verification methodologies (e.g. UVM, VMM, OVM)

  • C, C++, Perl, Python, and/or TCL

  • Design and Verification tools: simulation tools and debug tools (e.g. Quartus, Vivado, ModelSim, VCS, etc.)

Preferred Qualifications

  • 10+ years of experience of ASIC or FPGA, IP design, and/or Design Verification

  • Experience with protocol IP: Ethernet/PCIe

  • Experience with building block and system level testbench from scratch using System Verilog, experienced in UVM constrained random coverage driven concepts, assertion-based verification, and functional coverage techniques.

  • Experience in architecting test bench environments for unit and system level verification

  • End-to-end System level experience including design, software, firmware, and hardware

  • Experience working with customers and their systems, and providing optimized solutions.

Inside this Business Group

The Programmable Solutions Group (PSG) was formed from the acquisition of Altera. As part of Intel, PSG will create market-leading programmable logic devices that deliver a wider range of capabilities than customers experience today. Combining Altera's industry-leading FPGA technology and customer support with Intel's world-class semiconductor manufacturing capabilities will enable customers to create the next generation of electronic systems with unmatched performance and power efficiency. PSG takes pride in creating an energetic and dynamic work environment that is driven by ingenuity and innovation. We believe the growth and success of our group is directly linked to the growth and satisfaction of our employees. That is why PSG is committed to a work environment that is flexible and collaborative, and allows our employees to reach their full potential.

Other Locations

US, California, Santa Clara

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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Design Verification Engineer

San Jose, CA 95113

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