Design Verification and Methodology Engineer

San Jose, CA 95113
  • Job Code
Job Description

As a Design Verification and Methodology Engineer you will be responsible for the development and maintenance of tools developed within FPGA engineering for the automation and management of FPGA verification activities such as simulation, emulation and regressions. You will also be responsible for the development and maintenance of verification IP libraries used by engineering for the rapid development of test benches and environments for the verification of FPGA silicon and its IP portfolio. We are looking for someone with strong communication skills in order to understand the challenges that pre-silicon verification teams currently face with verification flows and methodologies, orchestrate solutions, and align the team to these solutions.


You must possess the below minimum education requirements and minimum required qualifications to be initially considered for this position. Relevant experience can be obtained through schoolwork, classes, project work, internships, and/or military experience. Additional preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.


Bachelors Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field

Minimum Qualifications

7+ years of experience. Experience should include:

  • Software programming such as Python, object-oriented programming, and use of open-source libraries, creating web pages, SQL and/or MongoDB

  • Pre-silicon design verification methodologies and flows using SystemVerilog and OVM/UVM with reg models

  • EDA tools such as Synopsys, VCS, etc. for simulation

Preferred Qualifications

  • 10+ years of experience.

  • Experience with Git and Perforce

  • Experience with software technologies such as XML/JSON/YAML exchange formats, databases including MongoDB, and REST API

  • Experience of digital logic design, computer architecture and networking

  • Experience with formal verification

  • Experience with emulators/emulation

Inside this Business Group

The Programmable Solutions Group (PSG) was formed from the acquisition of Altera. As part of Intel, PSG will create market-leading programmable logic devices that deliver a wider range of capabilities than customers experience today. Combining Altera's industry-leading FPGA technology and customer support with Intel's world-class semiconductor manufacturing capabilities will enable customers to create the next generation of electronic systems with unmatched performance and power efficiency. PSG takes pride in creating an energetic and dynamic work environment that is driven by ingenuity and innovation. We believe the growth and success of our group is directly linked to the growth and satisfaction of our employees. That is why PSG is committed to a work environment that is flexible and collaborative, and allows our employees to reach their full potential.

Other Locations

US, California, Santa Clara;US, Texas, Austin

Intel Corporation will require all new U.S. employees to be fully-vaccinated for Covid-19 as a condition of hire unless they have an approved accommodation in place under applicable law. Newly-hired employees will be required to provide proof of vaccination prior to their start date.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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Design Verification and Methodology Engineer

San Jose, CA 95113

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