Design Engineer - IP Integration

Intel
San Jose, CA 95113
  • Job Code
    JR0189803
Job Description

In this position you will be part of a world class Ethernet IP & SOC design team responsible for the design and development of the Ethernet Controllers and Networking Processing of the Network Division Silicon Engineering team. This is a great opportunity to join a talented team as a Design Engineer. 

Join the connectivity group, a high-performance technology team that is unleashing data center performance through innovation in end-to-end connectivity.

We are customer obsessed and fearless.  We believe in One Intel, diversity, and inclusion.


Quality, Truth & Transparency drive what we do every day. 

Responsibilities include but are not limited to:

  • Perform IP top-level Integration
  • ASIC tool enablement and methodology
  • Interfacing with cross-functional teams in DFT (design for test) and physical design. 

The ideal candidate will have the following skills and behavioral traits in addition to the qualifications listed below.

  • Takes initiative and is tenacious about learning
  • Works well on a team
  • Strong written and verbal communication skills


Qualifications

You must possess the below minimum education requirements and minimum required qualifications to be initially considered for this position. Additional preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Education Requirement:

The candidate must possess a Bachelor's degree in Computer Science, Computer Engineering, Electrical Engineering, Math, Physics, or related field with 3 plus years of experience, OR Master's in Computer Science, Computer Engineering, Electrical Engineering, Math, Physics, or related field with 2 plus years of experience. OR PhD in Computer Science, Computer Engineering, Electrical Engineering, Math, Physics, or related field in addition to the following:

Minimum Required Qualifications:   

  • 3 plus years experience programming in a scripting language like Python or Perl
  • 2 plus years experience with GIT Repository
  • 3 plus years experience with VCS compilation

Additional Preferred Qualifications:

  • 3 plus years experience with ASIC flow and methodology
  • 3 plus years experience with code coverage
  • 2 plus years experience with UPF
  • 1 plus years experience with DFx
  • 1 plus experience with Collage, Synopsys core builder
  • 2 plus years experience with x-prop

Inside this Business Group

The Data Center Group (DCG) is at the heart of Intels transformation from a PC company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologiesspanning software, processors, storage, I/O, and networking solutionsthat fuel cloud, communications, enterprise, and government data centers around the world.



Other Locations

US, California, Santa Clara;US, Oregon, Hillsboro


Intel Corporation will require all new U.S. employees to be fully-vaccinated for Covid-19 as a condition of hire unless they have an approved accommodation in place under applicable law. Newly-hired employees will be required to provide proof of vaccination prior to their start date.



Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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Design Engineer - IP Integration

Intel
San Jose, CA 95113

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